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| author | Matt DeVillier <matt.devillier@gmail.com> | 2017-04-17 18:47:16 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-02 18:29:45 +0200 |
| commit | fab0a49019146c7273adacad3b77445493581a9a (patch) | |
| tree | 4841ed3a1ad78bad71f93f26bf9c66daec96abf6 /src/soc | |
| parent | f9c46f0ebced9e750e4df05e33ebbaa7b7073aa4 (diff) | |
| download | coreboot-fab0a49019146c7273adacad3b77445493581a9a.tar.xz | |
soc/baytrail: add ACPI method to generate USB port info
Add ACPI method GPLD to generate port location data when
passed visiblity info. Will be used by _PLD method in
board-specific USB .asl files.
Change-Id: Iad947ae2cd541d3407455b218c2b352b9a373718
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19973
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/baytrail/acpi/xhci.asl | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/acpi/xhci.asl b/src/soc/intel/baytrail/acpi/xhci.asl index bef0b9ff2f..d3c0083c2f 100644 --- a/src/soc/intel/baytrail/acpi/xhci.asl +++ b/src/soc/intel/baytrail/acpi/xhci.asl @@ -23,6 +23,23 @@ Device (XHCI) Device (RHUB) { Name (_ADR, 0x00000000) + + // GPLD: Generate Port Location Data (PLD) + Method (GPLD, 1, Serialized) { + Name (PCKG, Package (0x01) { + Buffer (0x10) {} + }) + + // REV: Revision 0x02 for ACPI 5.0 + CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) + Store (0x02, REV) + + // VISI: Port visibility to user per port + CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) + Store (Arg0, VISI) + Return (PCKG) + } + Device (PRT1) { Name (_ADR, 1) } Device (PRT2) { Name (_ADR, 2) } Device (PRT3) { Name (_ADR, 3) } |