soc/intel/cannonlake: Add minimal changes to call FSP Memoryinit

The following minimal changes are needed to make system boot until FSP
memoryinit got called.
1. Program SA BARs
2. Assume previous power state is S0.

Change-Id: Iab96b27d4220acf4089b901bca28018eaba940a1
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

7 files changed, 195 insertions, 5 deletions

diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 27c2e9b864..480e0477ad 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -1,5 +1,6 @@
 ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y)
 
+subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/x86/mtrr
 subdirs-y += ../../../cpu/x86/tsc
diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h
index 9c7c41a91e..d69250776c 100644
--- a/src/soc/intel/cannonlake/include/soc/pm.h
+++ b/src/soc/intel/cannonlake/include/soc/pm.h
@@ -1,7 +1,8 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -13,9 +14,26 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _SOC_CANNONLAKE_PM_H_
-#define _SOC_CANNONLAKE_PM_H_
+#ifndef _SOC_PM_H_
+#define _SOC_PM_H_
 
-/* nothing here yet. Thanks for looking, though! */
+#include <arch/acpi.h>
+#include <soc/pmc.h>
 
-#endif
\ No newline at end of file
+struct chipset_power_state {
+	uint16_t pm1_sts;
+	uint16_t pm1_en;
+	uint32_t pm1_cnt;
+	uint16_t tco1_sts;
+	uint16_t tco2_sts;
+	uint32_t gpe0_sts[4];
+	uint32_t gpe0_en[4];
+	uint32_t gen_pmcon_a;
+	uint32_t gen_pmcon_b;
+	uint32_t gblrst_cause[2];
+	uint32_t prev_sleep_state;
+} __attribute__ ((packed));
+
+struct chipset_power_state *fill_power_state(void);
+
+#endif
diff --git a/src/soc/intel/cannonlake/include/soc/romstage.h b/src/soc/intel/cannonlake/include/soc/romstage.h
new file mode 100644
index 0000000000..2cdbaa57c1
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/romstage.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_ROMSTAGE_H_
+#define _SOC_ROMSTAGE_H_
+
+#include <arch/cpu.h>
+#include <fsp/api.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd);
+void systemagent_early_init(void);
+
+#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/cannonlake/romstage/Makefile.inc b/src/soc/intel/cannonlake/romstage/Makefile.inc
new file mode 100644
index 0000000000..99bc25f20e
--- /dev/null
+++ b/src/soc/intel/cannonlake/romstage/Makefile.inc
@@ -0,0 +1,18 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015-2017 Intel Corporation
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+romstage-y += power_state.c
+romstage-y += romstage.c
+romstage-y += systemagent.c
diff --git a/src/soc/intel/cannonlake/romstage/power_state.c b/src/soc/intel/cannonlake/romstage/power_state.c
new file mode 100644
index 0000000000..2c98a9e5ac
--- /dev/null
+++ b/src/soc/intel/cannonlake/romstage/power_state.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/early_variables.h>
+#include <arch/io.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <soc/pm.h>
+
+static struct chipset_power_state power_state CAR_GLOBAL;
+
+/* Fill power state structure from ACPI PM registers */
+struct chipset_power_state *fill_power_state(void)
+{
+	struct chipset_power_state *ps = car_get_var_ptr(&power_state);
+
+	return ps;
+}
+
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
new file mode 100644
index 0000000000..2604f29576
--- /dev/null
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <fsp/util.h>
+#include <memory_info.h>
+#include <soc/pm.h>
+#include <soc/romstage.h>
+#include <timestamp.h>
+
+asmlinkage void car_stage_entry(void)
+{
+	bool s3wake;
+	struct chipset_power_state *ps;
+
+	console_init();
+
+	/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
+	systemagent_early_init();
+
+	ps = fill_power_state();
+	timestamp_add_now(TS_START_ROMSTAGE);
+	s3wake = ps->prev_sleep_state == ACPI_S3;
+	fsp_memory_init(s3wake);
+	die("Get out from FSP memoryinit. \n");
+}
+
+void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
+{
+	mainboard_memory_init_params(mupd);
+}
+
+__attribute__((weak)) void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	/* Do nothing */
+}
\ No newline at end of file
diff --git a/src/soc/intel/cannonlake/romstage/systemagent.c b/src/soc/intel/cannonlake/romstage/systemagent.c
new file mode 100644
index 0000000000..f7c7f1a632
--- /dev/null
+++ b/src/soc/intel/cannonlake/romstage/systemagent.c
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <intelblocks/systemagent.h>
+#include <soc/iomap.h>
+#include <soc/romstage.h>
+#include <soc/systemagent.h>
+
+void systemagent_early_init(void)
+{
+	static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = {
+		{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
+		{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
+		{ EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
+	};
+
+	static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = {
+		{ REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
+		{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
+	};
+
+	/* Set Fixed MMIO addresss into PCI configuration space */
+	sa_set_pci_bar(soc_fixed_pci_resources,
+		       ARRAY_SIZE(soc_fixed_pci_resources));
+	/* Set Fixed MMIO addresss into MCH base address */
+	sa_set_mch_bar(soc_fixed_mch_resources,
+		       ARRAY_SIZE(soc_fixed_mch_resources));
+	/* Enable PAM regisers */
+	enable_pam_region();
+}