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authorAaron Durbin <adurbin@chromium.org>2014-01-09 14:35:41 -0600
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-05-13 21:02:09 +0200
commit107b71c3a3101c307acadb75c1e1e2f7b96c5015 (patch)
tree133d3bb5b38c810a2c8d38966afbdbe267cadfdf /src/soc
parent9f1a7cffabacdb6022e4579a6229eb5d29e9bcf4 (diff)
downloadcoreboot-107b71c3a3101c307acadb75c1e1e2f7b96c5015.tar.xz
baytrail: reboot with EC in S0 with no MRC cache and EC in RW
This improves boot time in 2 ways for a firmware upgrade: 1. Normally MRC would detect the S0 state without an MRC cache even though it's told to the S5 path. When it observes this state a cold reset occurs. The cold reset stays in S5 for at least 4 seconds which is time observed by the end user. 2. As the EC was running RW code before the reset after firmware upgrade it will still be running the older RW code. Vboot will then reboot the EC and the whole system to put the EC into RO mode so it can handle the RW update. The issues are mitigated by detecting the system is in S0 with no MRC cache and the EC isn't in RO mode. Therefore we can do the reboot without waiting the 4 secs and the EC is running RO so the 2nd reboot is not necessary. BUG=chrome-os-partner:24133 BRANCH=rambi,squawks TEST=Booted. Updated firmware while in OS. Rebooted. Noted the EC reboot before MRC execution. Change-Id: I1c53d334a5e18c237a74ffbe96f263a7540cd8fe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182061 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5040 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/baytrail/romstage/raminit.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index 352b86ffa2..752a49b1ff 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -32,6 +32,8 @@
#include <baytrail/pci_devs.h>
#include <baytrail/reset.h>
#include <baytrail/romstage.h>
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
static void reset_system(void)
{
@@ -131,6 +133,12 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
reset_system();
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
+#if CONFIG_EC_GOOGLE_CHROMEEC
+ if (prev_sleep_state == 0) {
+ /* Ensure EC is running RO firmware. */
+ google_chromeec_check_ec_image(EC_IMAGE_RO);
+ }
+#endif
}
mrc_entry = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab,