soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4G

This change sets the base for MMIO above 4G to TOUDD. It matches what
is used by resource allocator if MMIO resources are allocated above 4G
and also matches the expectation in northbridge.asl. This change
also gets rid of the macro ABOVE_4GB_MEM_BASE_ADDRESS since it is now
unused.

BUG=b:149186922
TEST=Verified that kernel does not complain about MMIO windows above
4G.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ibbbfbdad867735a43cf57c256bf206a3f040f383
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41155
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

7 files changed, 31 insertions, 34 deletions

diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h
index 49cdaca7ac..e79331a3e8 100644
--- a/src/soc/intel/apollolake/include/soc/iomap.h
+++ b/src/soc/intel/apollolake/include/soc/iomap.h
@@ -45,7 +45,6 @@
 #define EARLY_I2C_BASE_ADDRESS		0xfe020000
 #define EARLY_I2C_BASE(x)	(EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
 
-#define ABOVE_4GB_MEM_BASE_ADDRESS	(128ULL * GiB)
 #define ABOVE_4GB_MEM_BASE_SIZE	(64ULL * GiB)
 
 #endif /* _SOC_APOLLOLAKE_IOMAP_H_ */
diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h
index ec60d0bb8a..9d13d84d3a 100644
--- a/src/soc/intel/cannonlake/include/soc/iomap.h
+++ b/src/soc/intel/cannonlake/include/soc/iomap.h
@@ -54,7 +54,6 @@
 
 #define HECI1_BASE_ADDRESS	0xfeda2000
 
-#define ABOVE_4GB_MEM_BASE_ADDRESS	(256ULL * GiB)
 #define ABOVE_4GB_MEM_BASE_SIZE	(256ULL * GiB)
 
 /* PTT registers */
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index e7230bcbf4..3da837c0af 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -41,34 +41,6 @@ __weak unsigned long sa_write_acpi_tables(const struct device *dev,
 }
 
 /*
- * This function will get above 4GB mmio enable config specific to soc.
- *
- * Return values:
- *  0 = Above 4GB memory is not enable
- *  1 = Above 4GB memory is enable
- */
-static int get_enable_above_4GB_mmio(void)
-{
-	const struct soc_intel_common_config *common_config;
-	common_config = chip_get_common_soc_structure();
-
-	return common_config->enable_above_4GB_mmio;
-}
-
-/* Fill MMIO resource above 4GB into GNVS */
-void sa_fill_gnvs(global_nvs_t *gnvs)
-{
-	if (get_enable_above_4GB_mmio()) {
-		gnvs->e4gm = 1;
-		gnvs->a4gb = ABOVE_4GB_MEM_BASE_ADDRESS;
-		gnvs->a4gs = ABOVE_4GB_MEM_BASE_SIZE;
-		printk(BIOS_DEBUG,
-			"PCI space above 4GB MMIO is from 0x%llx  to len = 0x%llx\n",
-				gnvs->a4gb, gnvs->a4gs);
-	}
-}
-
-/*
  * Add all known fixed MMIO ranges that hang off the host bridge/memory
  * controller device.
  */
@@ -124,6 +96,37 @@ static void sa_read_map_entry(struct device *dev,
 	*result = value;
 }
 
+/*
+ * This function will get above 4GB mmio enable config specific to soc.
+ *
+ * Return values:
+ *  0 = Above 4GB memory is not enable
+ *  1 = Above 4GB memory is enable
+ */
+static int get_enable_above_4GB_mmio(void)
+{
+	const struct soc_intel_common_config *common_config;
+	common_config = chip_get_common_soc_structure();
+
+	return common_config->enable_above_4GB_mmio;
+}
+
+/* Fill MMIO resource above 4GB into GNVS */
+void sa_fill_gnvs(global_nvs_t *gnvs)
+{
+	if (!get_enable_above_4GB_mmio())
+		return;
+
+	struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
+
+	gnvs->e4gm = 1;
+	sa_read_map_entry(sa_dev, &sa_memory_map[SA_TOUUD_REG], &gnvs->a4gb);
+	gnvs->a4gs = ABOVE_4GB_MEM_BASE_SIZE;
+	printk(BIOS_DEBUG, "PCI space above 4GB MMIO is from 0x%llx  to len = 0x%llx\n",
+	       gnvs->a4gb, gnvs->a4gs);
+}
+
+
 static void sa_get_mem_map(struct device *dev, uint64_t *values)
 {
 	int i;
diff --git a/src/soc/intel/icelake/include/soc/iomap.h b/src/soc/intel/icelake/include/soc/iomap.h
index 06f68f0d60..6971a3d564 100644
--- a/src/soc/intel/icelake/include/soc/iomap.h
+++ b/src/soc/intel/icelake/include/soc/iomap.h
@@ -48,7 +48,6 @@
 #define VTD_BASE_ADDRESS	0xFED90000
 #define VTD_BASE_SIZE		0x00004000
 
-#define ABOVE_4GB_MEM_BASE_ADDRESS	(256ULL * GiB)
 #define ABOVE_4GB_MEM_BASE_SIZE	(256ULL * GiB)
 
 /*
diff --git a/src/soc/intel/jasperlake/include/soc/iomap.h b/src/soc/intel/jasperlake/include/soc/iomap.h
index f2300a2ee8..3ee06a2d2f 100644
--- a/src/soc/intel/jasperlake/include/soc/iomap.h
+++ b/src/soc/intel/jasperlake/include/soc/iomap.h
@@ -70,7 +70,6 @@
 #define VTD_BASE_ADDRESS	0xfed90000
 #define VTD_BASE_SIZE		0x00004000
 
-#define ABOVE_4GB_MEM_BASE_ADDRESS	(256ULL * GiB)
 #define ABOVE_4GB_MEM_BASE_SIZE	(256ULL * GiB)
 
 #define MCH_BASE_ADDRESS	0xfea80000
diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h
index afded553f5..a3db5c033e 100644
--- a/src/soc/intel/skylake/include/soc/iomap.h
+++ b/src/soc/intel/skylake/include/soc/iomap.h
@@ -61,7 +61,6 @@
 #define PTT_TXT_BASE_ADDRESS	0xfed30800
 #define PTT_PRESENT		0x00070000
 
-#define ABOVE_4GB_MEM_BASE_ADDRESS	(128ULL * GiB)
 #define ABOVE_4GB_MEM_BASE_SIZE	(64ULL * GiB)
 
 /*
diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h
index 13583d5257..70f908d57d 100644
--- a/src/soc/intel/tigerlake/include/soc/iomap.h
+++ b/src/soc/intel/tigerlake/include/soc/iomap.h
@@ -76,7 +76,6 @@
 #define VTD_BASE_ADDRESS	0xfed90000
 #define VTD_BASE_SIZE		0x00004000
 
-#define ABOVE_4GB_MEM_BASE_ADDRESS	(256ULL * GiB)
 #define ABOVE_4GB_MEM_BASE_SIZE	(256ULL * GiB)