diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2016-09-06 18:48:19 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-28 22:01:01 +0200 |
| commit | 28821dbb2261267462a7e9b0cc1c23b51af2d3ee (patch) | |
| tree | 98c2e5ea5d58afb11579c3bc4adeed895a576480 /src/soc | |
| parent | 9108680c1c17ec539bbba9525b6d9d62e57d296a (diff) | |
| download | coreboot-28821dbb2261267462a7e9b0cc1c23b51af2d3ee.tar.xz | |
soc/intel/apollolake: Add pmc_ipc device support
A dedicated pmc_ipc DSDT entry is required for pmc_ipc kernel driver.
The ACPI mode entry includes resources for PMC_IPC1, SRAM, ACPI IO and
Punit Mailbox.
BRANCH=None
BUG=chrome-os-partner:57364
TEST=Boot up into OS successfully and check with dmesg to see the
driver has been loaded successfully without errors.
Change-Id: I3f60999ab90962c4ea0a444812e4a7dcce1da5b6
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/16649
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/apollolake/acpi/pmc_ipc.asl | 57 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/acpi/southbridge.asl | 3 |
2 files changed, 60 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl new file mode 100644 index 0000000000..b89bebf5da --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/iomap.h> + +#define MAILBOX_DATA 0x7080 +#define MAILBOX_INTF 0x7084 +#define PMIO_LENGTH 0x80 + +Device (IPC1) +{ + Name (_HID, "INT34D2") + Name (_CID, "INT34D2") + Name (_DDN, "Intel(R) IPC1 Controller") + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x0, 0x2000, IBAR) + Memory32Fixed (ReadWrite, 0x0, 0x4, MDAT) + Memory32Fixed (ReadWrite, 0x0, 0x4, MINF) + IO (Decode16, ACPI_PMIO_BASE, ACPI_PMIO_BASE + PMIO_LENGTH, + 0x04, PMIO_LENGTH) + Memory32Fixed (ReadWrite, 0x0, 0x2000, SBAR) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) + { + PMC_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^IBAR._BAS, IBAS) + Store (PMC_BAR0, IBAS) + + CreateDwordField (^RBUF, ^MDAT._BAS, MDBA) + Store (MCH_BASE_ADDR + MAILBOX_DATA, MDBA) + CreateDwordField (^RBUF, ^MINF._BAS, MIBA) + Store (MCH_BASE_ADDR + MAILBOX_INTF, MIBA) + + CreateDwordField (^RBUF, ^SBAR._BAS, SBAS) + Store (PMC_SRAM_BASE_0, SBAS) + + Return (^RBUF) + } +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 1c10f1a5ed..f2b09c74eb 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -40,6 +40,9 @@ Scope (\_SB) #include "xhci.asl" +/* PMC IPC */ +#include "pmc_ipc.asl" + /* LPC */ #include "lpc.asl" |