summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorJonathan Zhang <jonzhang@fb.com>2020-04-10 15:48:06 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-06-14 16:46:15 +0000
commit3a6d8fd88994725f19bfc0e5555cd1bdd6eef4f0 (patch)
treef0d448c5190ae5d9bb1b12b11030ca5d41e9400d /src/soc
parentc11059550342999c382385ef0059349802061a99 (diff)
downloadcoreboot-3a6d8fd88994725f19bfc0e5555cd1bdd6eef4f0.tar.xz
soc/intel/xeon_sp/cpx: configure FSP-M UPD parameters
Configure FSP-M UPD parameters. TESTED=Boot CPX-SP based server. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: I2d0762a742d8803c7396034e3244120c1e8ece67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/xeon_sp/cpx/romstage.c59
1 files changed, 54 insertions, 5 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c
index c9202306e4..cbaa006219 100644
--- a/src/soc/intel/xeon_sp/cpx/romstage.c
+++ b/src/soc/intel/xeon_sp/cpx/romstage.c
@@ -5,22 +5,71 @@
#include <soc/romstage.h>
#include "chip.h"
+void __weak mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ /* Default weak implementation */
+}
+
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;
- (void)m_cfg;
/*
* Currently FSP for CPX does not implement user-provided StackBase/Size
* properly. When KTI link needs to be trained, inter-socket communication
* library needs quite a bit of memory for its heap usage. However, location
* is hardcoded so this workaround is needed.
*/
- if (CONFIG_MAX_SOCKET > 1) {
- arch_upd->StackBase = (void *) 0xfe930000;
- arch_upd->StackSize = 0x70000;
- }
+ arch_upd->StackBase = (void *) 0xfe930000;
+ arch_upd->StackSize = 0x70000;
+
+ /* ErrorLevel - 0 (disable) to 8 (verbose) */
+ m_cfg->DebugPrintLevel = 8;
+
+ /* BoardId 0x1D is for CooperCity reference platform */
+ m_cfg->BoardId = 0x1D;
+
+ /* Bitmask for valid sockets supported by the board */
+ m_cfg->BoardTypeBitmask = 0x11111111;
+
+ m_cfg->mmiolSize = 0x0;
+ m_cfg->mmiohBase = 0x2000;
+
+ /* default: 0x1 (enable), set to 0x2 (auto) */
+ m_cfg->KtiPrefetchEn = 0x2;
+ /* default: all 8 sockets enabled */
+ for (int i = 2; i < 8; ++i)
+ m_cfg->KtiFpgaEnable[i] = 0;
+ /* default: 0x1 (enable), set to 0x0 (disable) */
+ m_cfg->IsKtiNvramDataReady = 0x0;
+
+ /*
+ * Sub Numa(Non-Uniform Memory Access) Clustering ID and NUMA memory Assignment
+ * default: 0x1 (enable), set to 0x0 (disable)
+ */
+ m_cfg->SncEn = 0x0;
+
+ /* default: 0x1 (enable), set to 0x2 (auto) */
+ m_cfg->DirectoryModeEn = 0x2;
+
+ /* default: 0x1 (enable), set to 0x0 (disable) */
+ m_cfg->WaSerializationEn = 0x0;
+
+ /* default: 0x0 (disable), set to 0x2 (auto) */
+ m_cfg->XptRemotePrefetchEn = 0x2;
+
+ /* default: 0x0 (disable), set to 0x1 (enable) */
+ m_cfg->highGap = 0x1;
+
+ /* the wait time in units of 1000us for PBSP to check in */
+ m_cfg->WaitTimeForPSBP = 0x7530;
+
+ m_cfg->OemHookPostTopologyDiscovery = 0xFFF7727B;
+ m_cfg->OemGetResourceMapUpdate = 0xFFF7727C;
+
+ /* Needed to avoid FSP-M reset. The default value of 0x01 is for MinPlatform */
+ m_cfg->PchAdrEn = 0x02;
mainboard_memory_init_params(mupd);
}