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authorFurquan Shaikh <furquan@google.com>2020-06-10 11:52:49 -0700
committerFurquan Shaikh <furquan@google.com>2020-06-13 06:49:30 +0000
commit3b03206426f852c87b6e1132bd51a016e57fdf69 (patch)
tree167080b89f6e2a9a1e6cb40565ff3de0d8d227f9 /src/soc
parent46514c2b877c29c2d7c2061a9785736e270c0c62 (diff)
downloadcoreboot-3b03206426f852c87b6e1132bd51a016e57fdf69.tar.xz
soc/amd/picasso: Add custom memlayout.ld file
This change copies src/arch/x86/memlayout.ld file to src/soc/amd/picasso/ and sets MEMLAYOUT_LD_FILE config variable to point to this newly added file. Unused elements from the memlayout.ld file are dropped and path to early_dram.ld is updated to include the one from src/arch/x86. BUG=b:155322763 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I59bf5f93b712407ddcc9fb8a46167936c6c28a76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/picasso/Kconfig4
-rw-r--r--src/soc/amd/picasso/memlayout.ld45
2 files changed, 49 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 2bd9c0975c..dba4e2fa59 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -56,6 +56,10 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_CF9_RESET
select SUPPORT_CPU_UCODE_IN_CBFS
+config MEMLAYOUT_LD_FILE
+ string
+ default "src/soc/amd/picasso/memlayout.ld"
+
config PRERAM_CBMEM_CONSOLE_SIZE
hex
default 0x1600
diff --git a/src/soc/amd/picasso/memlayout.ld b/src/soc/amd/picasso/memlayout.ld
new file mode 100644
index 0000000000..8b2390909e
--- /dev/null
+++ b/src/soc/amd/picasso/memlayout.ld
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <memlayout.h>
+#include <arch/header.ld>
+
+#define EARLY_MEMLAYOUT "src/arch/x86/early_ram.ld"
+
+SECTIONS
+{
+ /*
+ * It would be good to lay down RAMSTAGE, ROMSTAGE, etc consecutively
+ * like other architectures/chipsets it's not possible because of
+ * the linking games played during romstage creation by trying
+ * to find the final landing place in CBFS for XIP. Therefore,
+ * conditionalize with macros.
+ */
+#if ENV_RAMSTAGE
+ RAMSTAGE(CONFIG_RAMBASE, (CONFIG(RELOCATABLE_RAMSTAGE) ? 8M :
+ CONFIG_RAMTOP - CONFIG_RAMBASE))
+
+#elif ENV_ROMSTAGE
+ /* The 1M size is not allocated. It's just for basic size checking.
+ * Link at 32MiB address and rely on cbfstool to relocate to XIP. */
+ ROMSTAGE(CONFIG_ROMSTAGE_ADDR, 1M)
+
+ #include EARLY_MEMLAYOUT
+#elif ENV_SEPARATE_VERSTAGE
+ /* The 1M size is not allocated. It's just for basic size checking.
+ * Link at 32MiB address and rely on cbfstool to relocate to XIP. */
+ VERSTAGE(CONFIG_VERSTAGE_ADDR, 1M)
+
+ #include EARLY_MEMLAYOUT
+#elif ENV_BOOTBLOCK
+ BOOTBLOCK(CONFIG_X86_RESET_VECTOR - CONFIG_C_ENV_BOOTBLOCK_SIZE + 0x10,
+ CONFIG_C_ENV_BOOTBLOCK_SIZE)
+
+ #include EARLY_MEMLAYOUT
+#endif
+}
+
+#if ENV_BOOTBLOCK
+/* Bootblock specific scripts which provide more SECTION directives. */
+#include <cpu/x86/16bit/entry16.ld>
+#include <cpu/x86/16bit/reset16.ld>
+#endif /* ENV_BOOTBLOCK */