summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorDuncan Laurie <dlaurie@chromium.org>2014-07-31 10:41:56 -0700
committerMarc Jones <marc.jones@se-eng.com>2015-03-27 05:28:09 +0100
commit3ed4d39b5727587913f6c872772cefbd2d106c07 (patch)
tree0736284bf6f5ae6b1f62c308bdce6ca682ea08c0 /src/soc
parent1053f6571c3487375b80a591fc3dd6c4355162eb (diff)
downloadcoreboot-3ed4d39b5727587913f6c872772cefbd2d106c07.tar.xz
broadwell: Add config option to disable DSP power gating in D3
This is useful for debug and testing. BUG=chrome-os-partner:29649 BRANCH=None TEST=build and boot on samus Original-Change-Id: I9050e75fd7c308ebd97d196298c687f8b0f8f97d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210599 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 2831154af4f33717489cb0b62aef228fb8f7c2e2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie622df02d9ab219cefce5f11332e010b47e3ec6e Reviewed-on: http://review.coreboot.org/8947 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/broadwell/adsp.c20
-rw-r--r--src/soc/intel/broadwell/chip.h3
2 files changed, 18 insertions, 5 deletions
diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c
index 41372158a0..9ecbe95b41 100644
--- a/src/soc/intel/broadwell/adsp.c
+++ b/src/soc/intel/broadwell/adsp.c
@@ -69,12 +69,22 @@ static void adsp_init(struct device *dev)
/* Set D3 Power Gating Enable in D19:F0:A0 based on PCH type */
tmp32 = pci_read_config32(dev, ADSP_PCI_VDRTCTL0);
- if (pch_is_wpt()) {
- tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT;
- tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT;
+ if (config->adsp_d3_pg_disable) {
+ if (pch_is_wpt()) {
+ tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT;
+ tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT;
+ } else {
+ tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT;
+ tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT;
+ }
} else {
- tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT;
- tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT;
+ if (pch_is_wpt()) {
+ tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT;
+ tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT;
+ } else {
+ tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT;
+ tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT;
+ }
}
pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32);
diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h
index a3b716b3bc..e433483198 100644
--- a/src/soc/intel/broadwell/chip.h
+++ b/src/soc/intel/broadwell/chip.h
@@ -84,6 +84,9 @@ struct soc_intel_broadwell_config {
uint8_t sio_i2c0_voltage;
uint8_t sio_i2c1_voltage;
+ /* Disable ADSP power gating in D3 */
+ uint8_t adsp_d3_pg_disable;
+
/*
* Clock Disable Map:
* [21:16] = CLKOUT_PCIE# 5-0