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authorShreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>2020-11-05 12:06:29 -0800
committerFurquan Shaikh <furquan@google.com>2020-11-11 20:44:31 +0000
commit42b1d3fccfefb70f8158f0f604b4dc4d3a0d1be5 (patch)
tree3c6138c2f655b72fa80f2711fd1447e34e78942a /src/soc
parent0c32182dbacf5bbb454019cf8ed1a1192b52a225 (diff)
downloadcoreboot-42b1d3fccfefb70f8158f0f604b4dc4d3a0d1be5.tar.xz
mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS
Selecting USE_CAR_NEM_ENHANCED_V1 as of now. This selection in Kconfig programs IA32_L3_MASK_1 (0xc91) & IA32_L3_MASK_2 (0xc92). These will select ways for eviction & non-eviction. TGL will have to switch back to USE_CAR_NEM_ENHANCED_V2 once the IA32_L3_SF_MASK_1 (0x1891) & IA32_L3_SF_MASK_2 (0x1892) programming requirements are understood. Bug=b:171601324 BRANCH=volteer Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache. Change-Id: Ifc77856e26ab26f9fbb2693f70c751f43337421b Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/tigerlake/Kconfig3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index b276fb905f..f1ac774cd0 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -23,7 +23,8 @@ config CPU_SPECIFIC_OPTIONS
select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SMI_HANDLER
select IDT_IN_EVERY_STAGE
- select USE_CAR_NEM_ENHANCED_V2 if !INTEL_CAR_NEM
+ select USE_CAR_NEM_ENHANCED_V1 if !INTEL_CAR_NEM
+ select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
select IOAPIC