summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorKane Chen <kane.chen@intel.com>2014-08-21 10:36:17 -0700
committerMarc Jones <marc.jones@se-eng.com>2015-03-27 06:02:14 +0100
commit472d0cb4490dacf19a05b6d1f484f1876e34bd4c (patch)
treee05f693803f4b09ee97bc4538c0a949ed7610224 /src/soc
parent8c1fd781347079f86bd6017b92e310604e2b1276 (diff)
downloadcoreboot-472d0cb4490dacf19a05b6d1f484f1876e34bd4c.tar.xz
broadwell: fixed power gating enable for disabled sata port
The original code won't set power gating for disabled port correctly, due to it must be set before Lock BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus verify bit 24, 26 is set in RCBA(0x3a84) for samus Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Change-Id: Id78d391ac657665a972cb4fd1810df6304a5a6ab Original-Reviewed-on: https://chromium-review.googlesource.com/213561 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Kane Chen <kane.chen@intel.com> Original-Commit-Queue: Kane Chen <kane.chen@intel.com> (cherry picked from commit 066c8c81df8be9ae9ab7b33342a93b0b3ea7b240) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic7c87b04863f93de5665d72e0f95b4105b1d4d3b Reviewed-on: http://review.coreboot.org/8960 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/broadwell/finalize.c3
-rw-r--r--src/soc/intel/broadwell/lpc.c2
2 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c
index 4f7a5181ab..bf77a87a10 100644
--- a/src/soc/intel/broadwell/finalize.c
+++ b/src/soc/intel/broadwell/finalize.c
@@ -100,6 +100,9 @@ static void broadwell_finalize(void *unused)
reg_script_run_on_dev(SA_DEV_ROOT, system_agent_finalize_script);
reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script);
+ /* Lock */
+ RCBA32_OR(0x3a6c, 0x00000001);
+
/* Read+Write the following registers */
MCHBAR32(0x6030) = MCHBAR32(0x6030);
MCHBAR32(0x6034) = MCHBAR32(0x6034);
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 0e5a2605ac..d7a3e82747 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -350,8 +350,6 @@ static void pch_pm_init(struct device *dev)
if (RCBA32(FD) & PCH_DISABLE_ADSPD)
RCBA32_OR(0x2b1c, (1 << 29));
- /* Lock */
- RCBA32_OR(0x3a6c, 0x00000001);
}
static void pch_cg_init(device_t dev)