diff options
author | Martin Roth <martin@coreboot.org> | 2020-06-07 17:18:06 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2020-06-15 22:10:16 +0000 |
commit | 4883252912665f56c8e7801fe03a26594a1e9d5d (patch) | |
tree | 5614fb9d2caecfdb74d7566d829ead28bfc0a742 /src/soc | |
parent | baba3e961072bfb7ffb4f0031ada27046a58d29e (diff) | |
download | coreboot-4883252912665f56c8e7801fe03a26594a1e9d5d.tar.xz |
soc/amd/common/block/acpimmio: Update acpimmio for psp_verstage
Because the PSP maps the MMIO addresses that are used to non-
deterministic addresses, the accesses need to be able to find
the address at runtime.
BUG=b:158124527
TEST=Build & boot with Trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I68305e0f31956c57bfdee42025bdfe938703e82d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42061
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r-- | src/soc/amd/common/block/acpimmio/Makefile.inc | 8 | ||||
-rw-r--r-- | src/soc/amd/common/block/acpimmio/mmio_util_psp.c | 163 | ||||
-rw-r--r-- | src/soc/amd/common/block/include/amdblocks/acpimmio.h | 33 |
3 files changed, 202 insertions, 2 deletions
diff --git a/src/soc/amd/common/block/acpimmio/Makefile.inc b/src/soc/amd/common/block/acpimmio/Makefile.inc index 69253b9203..13864e4361 100644 --- a/src/soc/amd/common/block/acpimmio/Makefile.inc +++ b/src/soc/amd/common/block/acpimmio/Makefile.inc @@ -1,13 +1,17 @@ bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c -verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c -verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c + +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO),y) +verstage-$(CONFIG_ARCH_VERSTAGE_X86_32) += biosram.c +verstage-$(CONFIG_ARCH_VERSTAGE_X86_32) += mmio_util.c +verstage-$(CONFIG_ARCH_VERSTAGE_ARM) += mmio_util_psp.c +endif diff --git a/src/soc/amd/common/block/acpimmio/mmio_util_psp.c b/src/soc/amd/common/block/acpimmio/mmio_util_psp.c new file mode 100644 index 0000000000..75f71e4399 --- /dev/null +++ b/src/soc/amd/common/block/acpimmio/mmio_util_psp.c @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <arch/io.h> +#include <device/mmio.h> +#include <amdblocks/acpimmio.h> + +static uintptr_t iomux_bar; + +void iomux_set_bar(void *bar) +{ + iomux_bar = (uintptr_t)bar; +} + +u8 iomux_read8(u8 reg) +{ + return read8((void *)(iomux_bar + reg)); +} + +u16 iomux_read16(u8 reg) +{ + return read16((void *)(iomux_bar + reg)); +} + +u32 iomux_read32(u8 reg) +{ + return read32((void *)(iomux_bar + reg)); +} + +void iomux_write8(u8 reg, u8 value) +{ + write8((void *)(iomux_bar + reg), value); +} + +void iomux_write16(u8 reg, u16 value) +{ + write16((void *)(iomux_bar + reg), value); +} + +void iomux_write32(u8 reg, u32 value) +{ + write32((void *)(iomux_bar + reg), value); +} + +static uintptr_t misc_bar; + +void misc_set_bar(void *bar) +{ + misc_bar = (uintptr_t)bar; +} + +u8 misc_read8(u8 reg) +{ + return read8((void *)(misc_bar + reg)); +} + +u16 misc_read16(u8 reg) +{ + return read16((void *)(misc_bar + reg)); +} + +u32 misc_read32(u8 reg) +{ + return read32((void *)(misc_bar + reg)); +} + +void misc_write8(u8 reg, u8 value) +{ + write8((void *)(misc_bar + reg), value); +} + +void misc_write16(u8 reg, u16 value) +{ + write16((void *)(misc_bar + reg), value); +} + +void misc_write32(u8 reg, u32 value) +{ + write32((void *)(misc_bar + reg), value); +} + +static uintptr_t gpio_bar; + +void gpio_set_bar(void *bar) +{ + gpio_bar = (uintptr_t)bar; +} + +void *gpio_get_bar(void) +{ + return (void *)gpio_bar; +} + +static uintptr_t aoac_bar; + +void aoac_set_bar(void *bar) +{ + aoac_bar = (uintptr_t)bar; +} + +u8 aoac_read8(u8 reg) +{ + return read8((void *)(aoac_bar + reg)); +} + +void aoac_write8(u8 reg, u8 value) +{ + write8((void *)(aoac_bar + reg), value); +} + +static uintptr_t io_bar; + +void io_set_bar(void *bar) +{ + io_bar = (uintptr_t)bar; +} + +u8 io_read8(u16 reg) +{ + return read8((void *)(io_bar + reg)); +} + +void io_write8(u16 reg, u8 value) +{ + write8((void *)(io_bar + reg), value); +} + +/* PM registers are accessed a byte at a time via CD6/CD7 */ +uint8_t pm_io_read8(uint8_t reg) +{ + outb(reg, PM_INDEX); + return inb(PM_DATA); +} + +uint16_t pm_io_read16(uint8_t reg) +{ + return (pm_io_read8(reg + sizeof(uint8_t)) << 8) | pm_io_read8(reg); +} + +uint32_t pm_io_read32(uint8_t reg) +{ + return (pm_io_read16(reg + sizeof(uint16_t)) << 16) | pm_io_read16(reg); +} + +void pm_io_write8(uint8_t reg, uint8_t value) +{ + outb(reg, PM_INDEX); + outb(value, PM_DATA); +} + +void pm_io_write16(uint8_t reg, uint16_t value) +{ + pm_io_write8(reg, value & 0xff); + value >>= 8; + pm_io_write8(reg + sizeof(uint8_t), value & 0xff); +} + +void pm_io_write32(uint8_t reg, uint32_t value) +{ + pm_io_write16(reg, value & 0xffff); + value >>= 16; + pm_io_write16(reg + sizeof(uint16_t), value & 0xffff); +} diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 84a9360d1b..a0ab615840 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -100,6 +100,38 @@ void pm_io_write8(uint8_t reg, uint8_t value); void pm_io_write16(uint8_t reg, uint16_t value); void pm_io_write32(uint8_t reg, uint32_t value); +void iomux_set_bar(void *bar); +void *iomux_get_bar(void); +void misc_set_bar(void *bar); +void *misc_get_bar(void); +void gpio_set_bar(void *bar); +void *gpio_get_bar(void); +void aoac_set_bar(void *bar); +void *aoac_get_bar(void); +void io_set_bar(void *bar); +u8 io_read8(u16 reg); +void io_write8(u16 reg, u8 value); + + +#if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && ENV_SEPARATE_VERSTAGE) + +u8 iomux_read8(u8 reg); +u16 iomux_read16(u8 reg); +u32 iomux_read32(u8 reg); +void iomux_write8(u8 reg, u8 value); +void iomux_write16(u8 reg, u16 value); +void iomux_write32(u8 reg, u32 value); +u8 misc_read8(u8 reg); +u16 misc_read16(u8 reg); +u32 misc_read32(u8 reg); +void misc_write8(u8 reg, u8 value); +void misc_write16(u8 reg, u16 value); +void misc_write32(u8 reg, u32 value); +u8 aoac_read8(u8 reg); +void aoac_write8(u8 reg, u8 value); + +#else + static inline uint8_t sm_pci_read8(uint8_t reg) { return read8((void *)(ACPIMMIO_SM_PCI_BASE + reg)); @@ -515,4 +547,5 @@ static inline void aoac_write8(uint8_t reg, uint8_t value) write8((void *)(ACPIMMIO_AOAC_BASE + reg), value); } +#endif /* (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && ENV_SEPARATE_VERSTAGE) */ #endif /* __AMDBLOCKS_ACPIMMIO_H__ */ |