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authorSubrata Banik <subrata.banik@intel.com>2020-10-06 18:27:25 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-10-08 04:09:46 +0000
commit4929c358cc133f761fec2968fb4b1c823f72a9df (patch)
treeedf775b1f2d62d0c198c501d341b2e47660b9d79 /src/soc
parentad87b2a039153038feb2fdf03fd42b173e06db4a (diff)
downloadcoreboot-4929c358cc133f761fec2968fb4b1c823f72a9df.tar.xz
soc/intel: Make use of common gfx.asl
Add gfx.asl file for all IA SOCs to allow for graphics-related ACPI devices and methods. TEST=Able to build and boot TGL platform Dump and disassemble DSDT, verify GFX0 device present as below Device (GFX0) { Name (_ADR, 0x00020000) // _ADR: Address } Change-Id: I5560e900a77872552df1064dc3b7a8148e35d682 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/alderlake/acpi/southbridge.asl3
-rw-r--r--src/soc/intel/apollolake/acpi/southbridge.asl3
-rw-r--r--src/soc/intel/elkhartlake/acpi/southbridge.asl3
-rw-r--r--src/soc/intel/icelake/acpi/southbridge.asl3
-rw-r--r--src/soc/intel/jasperlake/acpi/southbridge.asl3
-rw-r--r--src/soc/intel/tigerlake/acpi/southbridge.asl3
6 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl
index 373dca5840..42f3b129a9 100644
--- a/src/soc/intel/alderlake/acpi/southbridge.asl
+++ b/src/soc/intel/alderlake/acpi/southbridge.asl
@@ -17,6 +17,9 @@
/* GPIO controller */
#include "gpio.asl"
+/* GFX 00:02.0 */
+#include <soc/intel/common/block/acpi/acpi/gfx.asl>
+
/* ESPI 0:1f.0 */
#include <soc/intel/common/block/acpi/acpi/lpc.asl>
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index f4d1497223..4a8be47c51 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -17,6 +17,9 @@
#include "xhci.asl"
+/* GFX 00:02.0 */
+#include <soc/intel/common/block/acpi/acpi/gfx.asl>
+
/* LPC */
#include <soc/intel/common/block/acpi/acpi/lpc.asl>
diff --git a/src/soc/intel/elkhartlake/acpi/southbridge.asl b/src/soc/intel/elkhartlake/acpi/southbridge.asl
index d85ddac77a..28705b1097 100644
--- a/src/soc/intel/elkhartlake/acpi/southbridge.asl
+++ b/src/soc/intel/elkhartlake/acpi/southbridge.asl
@@ -14,6 +14,9 @@
/* GPIO controller */
#include "gpio.asl"
+/* GFX 00:02.0 */
+#include <soc/intel/common/block/acpi/acpi/gfx.asl>
+
/* ESPI 0:1f.0 */
#include <soc/intel/common/block/acpi/acpi/lpc.asl>
diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl
index 4abea7c6f9..129a88da8c 100644
--- a/src/soc/intel/icelake/acpi/southbridge.asl
+++ b/src/soc/intel/icelake/acpi/southbridge.asl
@@ -17,6 +17,9 @@
/* GPIO controller */
#include "gpio.asl"
+/* GFX 00:02.0 */
+#include <soc/intel/common/block/acpi/acpi/gfx.asl>
+
/* ESPI 0:1f.0 */
#include <soc/intel/common/block/acpi/acpi/lpc.asl>
diff --git a/src/soc/intel/jasperlake/acpi/southbridge.asl b/src/soc/intel/jasperlake/acpi/southbridge.asl
index b68539aec7..b82cce50ab 100644
--- a/src/soc/intel/jasperlake/acpi/southbridge.asl
+++ b/src/soc/intel/jasperlake/acpi/southbridge.asl
@@ -17,6 +17,9 @@
/* GPIO controller */
#include "gpio.asl"
+/* GFX 00:02.0 */
+#include <soc/intel/common/block/acpi/acpi/gfx.asl>
+
/* ESPI 0:1f.0 */
#include <soc/intel/common/block/acpi/acpi/lpc.asl>
diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl
index 373dca5840..42f3b129a9 100644
--- a/src/soc/intel/tigerlake/acpi/southbridge.asl
+++ b/src/soc/intel/tigerlake/acpi/southbridge.asl
@@ -17,6 +17,9 @@
/* GPIO controller */
#include "gpio.asl"
+/* GFX 00:02.0 */
+#include <soc/intel/common/block/acpi/acpi/gfx.asl>
+
/* ESPI 0:1f.0 */
#include <soc/intel/common/block/acpi/acpi/lpc.asl>