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authorAamir Bohra <aamir.bohra@intel.com>2017-05-25 14:38:37 +0530
committerAaron Durbin <adurbin@chromium.org>2017-06-05 00:33:38 +0200
commit4c9cf304c7a4512bef50d266c21d7a5adeebe74a (patch)
tree136fef9596a30948312a34c3d069fb7f18df3f54 /src/soc
parent842776e1dcb310e889d2ba922be9d7b81a1c2dd0 (diff)
downloadcoreboot-4c9cf304c7a4512bef50d266c21d7a5adeebe74a.tar.xz
soc/intel/apollolake: Use Intel timer common code
Change-Id: I7b415711d01ddc0d998eba62de2c2139045efa80 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/apollolake/Kconfig1
-rw-r--r--src/soc/intel/apollolake/tsc_freq.c6
2 files changed, 1 insertions, 6 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index fe72c078f7..b0fd4b10a8 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -62,6 +62,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_RTC
select SOC_INTEL_COMMON_BLOCK_SA
+ select SOC_INTEL_COMMON_BLOCK_TIMER
select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_BLOCK_XDCI
select SOC_INTEL_COMMON_BLOCK_XHCI
diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c
index 885311c555..18d28d80f0 100644
--- a/src/soc/intel/apollolake/tsc_freq.c
+++ b/src/soc/intel/apollolake/tsc_freq.c
@@ -23,12 +23,6 @@
#include <delay.h>
#include "chip.h"
-unsigned long tsc_freq_mhz(void)
-{
- msr_t msr = rdmsr(MSR_PLATFORM_INFO);
- return (CONFIG_CPU_BCLK_MHZ * ((msr.lo >> 8) & 0xff));
-}
-
void set_max_freq(void)
{
msr_t msr, msr_rd;