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authorAngel Pons <th3fanbus@gmail.com>2020-10-25 00:38:50 +0000
committerAngel Pons <th3fanbus@gmail.com>2020-11-03 19:09:51 +0000
commit55a890fe3a4edede1580ab5c1d57dfe8e194e3f7 (patch)
tree7abc7e24db9d066bb2f0a8b9085d700b5e853677 /src/soc
parent3d8b6e25bbb688fee09f540ef331f4846b688669 (diff)
downloadcoreboot-55a890fe3a4edede1580ab5c1d57dfe8e194e3f7.tar.xz
Revert "broadwell: Switch to using common ACPI _SWS code"
This reverts commit 81a4c85acf664156bb68807f681cd40928bf8267. Reason for revert: Blocks merging Haswell and Broadwell together. Tested on out-of-tree Acer Aspire E5-573, still boots. Change-Id: I29c4ad9174ab84c7e9111daa0491ede9e1d639b4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46734 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/broadwell/Kconfig1
-rw-r--r--src/soc/intel/broadwell/acpi/platform.asl20
-rw-r--r--src/soc/intel/broadwell/ramstage.c59
3 files changed, 64 insertions, 16 deletions
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 2430be61f5..6e57f0aa8e 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -34,7 +34,6 @@ config CPU_SPECIFIC_OPTIONS
select TSC_MONOTONIC_TIMER
select SOC_INTEL_COMMON
select INTEL_DESCRIPTOR_MODE_CAPABLE
- select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT
select INTEL_GMA_ACPI
select HAVE_POWER_STATE_AFTER_FAILURE
diff --git a/src/soc/intel/broadwell/acpi/platform.asl b/src/soc/intel/broadwell/acpi/platform.asl
index f404352504..880b2061ec 100644
--- a/src/soc/intel/broadwell/acpi/platform.asl
+++ b/src/soc/intel/broadwell/acpi/platform.asl
@@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* Enable ACPI _SWS methods */
-#include <soc/intel/common/acpi/acpi_wake_source.asl>
#include <southbridge/intel/common/acpi/platform.asl>
/*
@@ -19,3 +17,21 @@ Method (_WAK, 1)
{
Return (Package (){ 0, 0 })
}
+
+Scope (\_SB)
+{
+ Method (_SWS)
+ {
+ /* Index into PM1 for device that caused wake */
+ Return (\PM1I)
+ }
+}
+
+Scope (\_GPE)
+{
+ Method (_SWS)
+ {
+ /* Index into GPE for device that caused wake */
+ Return (\GPEI)
+ }
+}
diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c
index c414d62192..57abf95207 100644
--- a/src/soc/intel/broadwell/ramstage.c
+++ b/src/soc/intel/broadwell/ramstage.c
@@ -2,32 +2,63 @@
#include <acpi/acpi.h>
#include <cbmem.h>
+#include <console/console.h>
#include <device/device.h>
#include <string.h>
#include <soc/nvs.h>
#include <soc/pm.h>
#include <soc/ramstage.h>
#include <soc/intel/broadwell/chip.h>
-#include <soc/intel/common/acpi.h>
-#include <assert.h>
-/* Save wake source information for calculating ACPI _SWS values */
-int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
+/* Save bit index for PM1_STS and GPE_STS for ACPI _SWS */
+static void save_acpi_wake_source(struct global_nvs *gnvs)
{
struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
- static uint32_t gpe0_sts[GPE0_REG_MAX];
- int i;
+ uint16_t pm1;
+ int gpe_reg;
- assert(ps != NULL);
+ if (!ps)
+ return;
+
+ pm1 = ps->pm1_sts & ps->pm1_en;
+
+ /* Scan for first set bit in PM1 */
+ for (gnvs->pm1i = 0; gnvs->pm1i < 16; gnvs->pm1i++) {
+ if (pm1 & 1)
+ break;
+ pm1 >>= 1;
+ }
+
+ /* If unable to determine then return -1 */
+ if (gnvs->pm1i >= 16)
+ gnvs->pm1i = -1;
+
+ /* Scan for first set bit in GPE registers */
+ gnvs->gpei = -1;
+ for (gpe_reg = 0; gpe_reg < GPE0_REG_MAX; gpe_reg++) {
+ u32 gpe = ps->gpe0_sts[gpe_reg] & ps->gpe0_en[gpe_reg];
+ int start = gpe_reg * GPE0_REG_SIZE;
+ int end = start + GPE0_REG_SIZE;
+
+ if (gpe == 0) {
+ if (!gnvs->gpei)
+ gnvs->gpei = end;
+ continue;
+ }
- *pm1 = ps->pm1_sts & ps->pm1_en;
+ for (gnvs->gpei = start; gnvs->gpei < end; gnvs->gpei++) {
+ if (gpe & 1)
+ break;
+ gpe >>= 1;
+ }
+ }
- /* Mask off GPE0 status bits that are not enabled */
- *gpe0 = &gpe0_sts[0];
- for (i = 0; i < GPE0_REG_MAX; i++)
- gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i];
+ /* If unable to determine then return -1 */
+ if (gnvs->gpei >= (GPE0_REG_MAX * GPE0_REG_SIZE))
+ gnvs->gpei = -1;
- return GPE0_REG_MAX;
+ printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %lld GPE Index %lld\n",
+ gnvs->pm1i, gnvs->gpei);
}
static void s3_resume_prepare(void)
@@ -40,6 +71,8 @@ static void s3_resume_prepare(void)
if (!acpi_is_wakeup_s3())
memset(gnvs, 0, sizeof(struct global_nvs));
+ else
+ save_acpi_wake_source(gnvs);
}
void broadwell_init_pre_device(void *chip_info)