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authorRichard Spiegel <richard.spiegel@amd.corp-partner.google.com>2018-08-24 16:48:20 -0700
committerMartin Roth <martinroth@google.com>2018-08-30 14:47:52 +0000
commit6635b3d9a1d81aeebb215e28cdf19be858dad3c3 (patch)
tree91d369ee3080d27c4ac154709a6510272a495882 /src/soc
parent8120759d90f7e5164a600f21bdd04b8878ba8259 (diff)
downloadcoreboot-6635b3d9a1d81aeebb215e28cdf19be858dad3c3.tar.xz
soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()
Function pci_ehci_dbg_set_port() used NDA register DEBUGPORT_MISC_CONTROL, which was deprecated in favor of a public PCI register (though only the bits to enable debug port became public) 0x90. Therefore code needs to be updated. BUG=b:69231009 TEST=Build and boot grunt. Change-Id: Ibb25992729d984b8570712f91a03a7cd1e9b8643 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/stoneyridge/enable_usbdebug.c17
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h5
2 files changed, 12 insertions, 10 deletions
diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c
index efe34e5141..81f60f0e9a 100644
--- a/src/soc/amd/stoneyridge/enable_usbdebug.c
+++ b/src/soc/amd/stoneyridge/enable_usbdebug.c
@@ -22,8 +22,6 @@
#include <device/pci_def.h>
#include <soc/southbridge.h>
-#define DEBUGPORT_MISC_CONTROL 0x80
-
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
{
/* Enable all of the USB controllers */
@@ -40,13 +38,12 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
{
- u8 *base_regs = pci_ehci_base_regs(dev);
- u32 reg32;
+ u32 reg32, value;
- /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
- reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL);
- reg32 &= ~(0xf << 28);
- reg32 |= (port << 28);
- reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
- write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
+ value = (port & 0x3) << DEBUG_PORT_SELECT_SHIFT;
+ value |= DEBUG_PORT_ENABLE;
+ reg32 = pci_read_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4);
+ reg32 &= ~DEBUG_PORT_MASK;
+ reg32 |= value;
+ pci_write_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4, reg32);
}
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 530b93a3e4..f054b3b61e 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -305,6 +305,11 @@
#define OC_PORT2_SHIFT 8
#define OC_PORT3_SHIFT 12
+#define EHCI_HUB_CONFIG4 0x90
+#define DEBUG_PORT_SELECT_SHIFT 16
+#define DEBUG_PORT_ENABLE BIT(18)
+#define DEBUG_PORT_MASK (BIT(16) | BIT(17) | (BIT(18))
+
#define WIDEIO_RANGE_ERROR -1
#define TOTAL_WIDEIO_PORTS 3