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authorJohn Zhao <john.zhao@intel.com>2020-09-01 15:04:18 -0700
committerDuncan Laurie <dlaurie@chromium.org>2020-10-05 22:41:16 +0000
commit6e8d38ec4e6a5a89e1bf6cec611d5bf8d47b215d (patch)
tree4f2d847fa85c6b29b63b2c986477668bdb7e2243 /src/soc
parentab2ad3f2f940199c289a889c3eedebc1b02a929b (diff)
downloadcoreboot-6e8d38ec4e6a5a89e1bf6cec611d5bf8d47b215d.tar.xz
soc/intel/tigerlake: Update TCSS PM flow
There is requirement to change PM flow for S0ix along with TBT firmware update under device attached and no device attached scenarios. This change invokes D3CE and D3CX in DMA _PS3 and _PS0 respectively. BUG=b:158777291 TEST=Validated s0ix cycles for USB4 device attached and no device attached test cases along with updated TBT firmware rev35. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Iebc8065fe4c8600960d089577608890ab12a95fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/45014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/tigerlake/acpi/tcss_dma.asl30
-rw-r--r--src/soc/intel/tigerlake/acpi/tcss_pcierp.asl22
2 files changed, 29 insertions, 23 deletions
diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl
index da2e8fe97d..f7c4117dcf 100644
--- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl
@@ -32,20 +32,12 @@ Method (_S0W, 0x0)
Method (_PR0)
{
- If (DUID == 0) {
- Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
- } Else {
- Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
- }
+ Return (Package() { \_SB.PCI0.D3C })
}
Method (_PR3)
{
- If (DUID == 0) {
- Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
- } Else {
- Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
- }
+ Return (Package() { \_SB.PCI0.D3C })
}
/*
@@ -72,6 +64,24 @@ Method (D3CE, 0, Serialized)
*/
Name (SD3C, 0)
+Method (_PS0, 0, Serialized)
+{
+ If (DUID == 0) {
+ \_SB.PCI0.TBT0._ON()
+ } Else {
+ \_SB.PCI0.TBT1._ON()
+ }
+}
+
+Method (_PS3, 0, Serialized)
+{
+ If (DUID == 0) {
+ \_SB.PCI0.TBT0._OFF()
+ } Else {
+ \_SB.PCI0.TBT1._OFF()
+ }
+}
+
Method (_DSW, 3)
{
/* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */
diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
index abca5d1607..b4c0cefa1e 100644
--- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
@@ -76,10 +76,14 @@ Device (PXSX)
Method (_DSW, 3)
{
- C2PM (Arg0, Arg1, Arg2, DCPM)
/* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */
- \_SB.PCI0.TDM0.SD3C = Arg1
- \_SB.PCI0.TDM1.SD3C = Arg1
+ If ((TUID == 0) || (TUID == 1)) {
+ \_SB.PCI0.TDM0.SD3C = Arg1
+ } Else {
+ \_SB.PCI0.TDM1.SD3C = Arg1
+ }
+
+ C2PM (Arg0, Arg1, Arg2, DCPM)
}
Method (_PRW, 0)
@@ -302,20 +306,12 @@ Method (_S0W, 0x0, NotSerialized)
Method (_PR0)
{
- If ((TUID == 0) || (TUID == 1)) {
- Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
- } Else {
- Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
- }
+ Return (Package() { \_SB.PCI0.D3C })
}
Method (_PR3)
{
- If ((TUID == 0) || (TUID == 1)) {
- Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
- } Else {
- Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
- }
+ Return (Package() { \_SB.PCI0.D3C })
}
/*