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authorAaron Durbin <adurbin@chromium.org>2014-08-13 16:19:59 -0500
committerPatrick Georgi <pgeorgi@google.com>2015-03-26 00:27:20 +0100
commit703159aca50dc60cdcd12a3fd80262d0e5372860 (patch)
tree6d21115ed00b36571f4bc4e14cf40f68dcf0bc74 /src/soc
parentedb58fd2aa2d0f12c459bc94dc5b3d497e648eaa (diff)
downloadcoreboot-703159aca50dc60cdcd12a3fd80262d0e5372860.tar.xz
tegra132: add usb initialization support to funit
Continuing down the path of easing mainboard maintenance provide a way to bring up the USB 2.0 ports through funit. BUG=chrome-os-partner:31251 BRANCH=None TEST=With ryu patch was able to get same sporadic USB communication. Change-Id: Ic75821acf1d48a9f1659849fa007251c61658640 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5183c5081a95219f84c4d6dfca70926b383abc1a Original-Change-Id: Iee5ca30b3c8b876a9cae7b91db096fef933a8412 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212332 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8938 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/nvidia/tegra132/Makefile.inc2
-rw-r--r--src/soc/nvidia/tegra132/funitcfg.c25
-rw-r--r--src/soc/nvidia/tegra132/include/soc/funitcfg.h10
3 files changed, 36 insertions, 1 deletions
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index 0411f74b59..000e295ad3 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -15,6 +15,7 @@ bootblock-y += ../tegra/i2c.c
bootblock-y += ../tegra/pingroup.c
bootblock-y += ../tegra/pinmux.c
bootblock-y += ../tegra/apbmisc.c
+bootblock-y += ../tegra/usb.c
ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
bootblock-$(CONFIG_DRIVERS_UART) += uart.c
endif
@@ -40,6 +41,7 @@ romstage-y += sdram_lp0.c
romstage-y += ../tegra/gpio.c
romstage-y += ../tegra/i2c.c
romstage-y += ../tegra/pinmux.c
+romstage-y += ../tegra/usb.c
romstage-$(CONFIG_DRIVERS_UART) += uart.c
ramstage-y += addressmap.c
diff --git a/src/soc/nvidia/tegra132/funitcfg.c b/src/soc/nvidia/tegra132/funitcfg.c
index e89670bfdf..9111f258d4 100644
--- a/src/soc/nvidia/tegra132/funitcfg.c
+++ b/src/soc/nvidia/tegra132/funitcfg.c
@@ -23,6 +23,7 @@
#include <soc/clock.h>
#include <soc/padconfig.h>
#include <string.h>
+#include <soc/nvidia/tegra/usb.h>
struct clk_dev_control {
uint32_t *clk_enb_set;
@@ -73,6 +74,14 @@ static const struct clk_dev_control clk_data_arr[] = {
.clk_enb_val = CLK_##clk_set_##_##funit_, \
}
+#define FUNIT_DATA_USB(funit_, clk_set_) \
+ [FUNIT_INDEX(funit_)] = { \
+ .name = STRINGIFY(funit_), \
+ .ctlr_base = (void *)(uintptr_t)TEGRA_##funit_##_BASE, \
+ .dev_control = &clk_data_arr[CLK_##clk_set_##_SET], \
+ .clk_enb_val = CLK_##clk_set_##_##funit_, \
+ }
+
static const struct funit_cfg_data funit_data[] = {
FUNIT_DATA(SBC1, sbc1, H),
FUNIT_DATA(SBC4, sbc4, U),
@@ -81,6 +90,9 @@ static const struct funit_cfg_data funit_data[] = {
FUNIT_DATA(I2C5, i2c5, H),
FUNIT_DATA(SDMMC3, sdmmc3, U),
FUNIT_DATA(SDMMC4, sdmmc4, L),
+ FUNIT_DATA_USB(USBD, L),
+ FUNIT_DATA_USB(USB2, H),
+ FUNIT_DATA_USB(USB3, H),
};
_Static_assert(ARRAY_SIZE(funit_data) == FUNIT_INDEX_MAX,
"funit_cfg_data array not filled out!");
@@ -129,6 +141,11 @@ static void configure_clock(const struct funit_cfg * const entry,
clk_div_mask, entry->clk_src_id);
}
+static inline int is_usb(uint32_t idx)
+{
+ return (idx == FUNIT_USBD || idx == FUNIT_USB2 || idx == FUNIT_USB3);
+}
+
void soc_configure_funits(const struct funit_cfg * const entries, size_t num)
{
size_t i;
@@ -137,6 +154,7 @@ void soc_configure_funits(const struct funit_cfg * const entries, size_t num)
const struct funit_cfg * const entry = &entries[i];
const struct funit_cfg_data *funit;
const struct clk_dev_control *dev_control;
+ int funit_usb = is_usb(entry->funit_index);
if (entry->funit_index >= FUNIT_INDEX_MAX) {
printk(BIOS_ERR, "Error: Index out of bounds\n");
@@ -146,12 +164,17 @@ void soc_configure_funits(const struct funit_cfg * const entries, size_t num)
funit = &funit_data[entry->funit_index];
dev_control = funit->dev_control;
- configure_clock(entry, funit);
+ /* USB controllers have a fixed clock source. */
+ if (!funit_usb)
+ configure_clock(entry, funit);
clock_grp_enable_clear_reset(funit->clk_enb_val,
dev_control->clk_enb_set,
dev_control->rst_dev_clr);
+ if (funit_usb)
+ usb_setup_utmip(funit->ctlr_base);
+
soc_configure_pads(entry->pad_cfg,entry->pad_cfg_size);
}
}
diff --git a/src/soc/nvidia/tegra132/include/soc/funitcfg.h b/src/soc/nvidia/tegra132/include/soc/funitcfg.h
index 0bb20a537d..7e9bdc0ee4 100644
--- a/src/soc/nvidia/tegra132/include/soc/funitcfg.h
+++ b/src/soc/nvidia/tegra132/include/soc/funitcfg.h
@@ -35,6 +35,9 @@ enum {
FUNIT_INDEX(I2C5),
FUNIT_INDEX(SDMMC3),
FUNIT_INDEX(SDMMC4),
+ FUNIT_INDEX(USBD),
+ FUNIT_INDEX(USB2),
+ FUNIT_INDEX(USB3),
FUNIT_INDEX_MAX,
};
@@ -55,6 +58,13 @@ struct funit_cfg {
.pad_cfg_size = _cfg_size, \
}
+#define FUNIT_CFG_USB(_funit) \
+ { \
+ .funit_index = FUNIT_INDEX(_funit), \
+ .pad_cfg = NULL, \
+ .pad_cfg_size = 0, \
+ }
+
/*
* Configure the funits associated with entry according to the configuration.
*/