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authorPhilipp Hug <philipp@hug.cx>2018-07-07 21:34:31 +0200
committerRonald G. Minnich <rminnich@gmail.com>2018-09-13 15:32:53 +0000
commit7524400242be26610df143b5d1d781f875239c45 (patch)
treea8055581b7f492e2bddbb8937f7649c043db33bd /src/soc
parent3e51d530645059093e6dd27c4bbfafb8a216cd41 (diff)
downloadcoreboot-7524400242be26610df143b5d1d781f875239c45.tar.xz
uart/sifive: make divisor configurable
The SiFive UART on the HiFive Unleashed uses the tlclk as input clock which runs at coreclk / 2. The input frequency is configured in the board code depending on the current stage. (bootblock + romstage run at 33.33Mhz, ramstage at 1Ghz) Change-Id: Iaf66723dba3d308f809fde5b05dfc3e43f43bd42 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/sifive/fu540/Kconfig2
-rw-r--r--src/soc/sifive/fu540/uart.c8
2 files changed, 9 insertions, 1 deletions
diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig
index c438a10162..457d16bb4e 100644
--- a/src/soc/sifive/fu540/Kconfig
+++ b/src/soc/sifive/fu540/Kconfig
@@ -20,7 +20,7 @@ config SOC_SIFIVE_FU540
select ARCH_RAMSTAGE_RISCV
select BOOTBLOCK_CONSOLE
select DRIVERS_UART_SIFIVE
-
+ select UART_OVERRIDE_REFCLK
if SOC_SIFIVE_FU540
config RISCV_ARCH
diff --git a/src/soc/sifive/fu540/uart.c b/src/soc/sifive/fu540/uart.c
index 940dc97856..c53f42d9d8 100644
--- a/src/soc/sifive/fu540/uart.c
+++ b/src/soc/sifive/fu540/uart.c
@@ -23,3 +23,11 @@ uintptr_t uart_platform_base(int idx)
else
return 0;
}
+
+unsigned int uart_platform_refclk(void)
+{
+ /*
+ * The SiFive UART uses tlclk, which is coreclk/2 as input
+ */
+ return 33330000 / 2;
+}