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| author | Angel Pons <th3fanbus@gmail.com> | 2020-12-05 20:43:00 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-12-11 15:12:47 +0000 |
| commit | 79b2a150c7a18a61604b0d81f52a7c6ad8522b60 (patch) | |
| tree | 35fdf0dcfa4e0eaf2605c4f0c62cf2690ebcd409 /src/soc | |
| parent | 30ff00650a7129475bf01ce9d258ac27b59c786b (diff) | |
| download | coreboot-79b2a150c7a18a61604b0d81f52a7c6ad8522b60.tar.xz | |
sb/intel/x/smbus.c: Factor out common code
Since common smbus.c gets built for romstage as well, create a new file
to hold this common code. Account for ICH7 not having a memory BAR, too.
Change-Id: I4ab46750c6fb7f71cbd55848e79ecc3e44cbbd04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48364
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
0 files changed, 0 insertions, 0 deletions