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| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-09-17 18:48:00 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-20 13:35:22 +0000 |
| commit | 8370f6b79c06bcea1a04f53e9028d0aa447e3583 (patch) | |
| tree | 99edaf4a20f07fc98c101db42997279adf7c8c32 /src/soc | |
| parent | dce635977381ff293f7f74c5cdfae142f36412d8 (diff) | |
| download | coreboot-8370f6b79c06bcea1a04f53e9028d0aa447e3583.tar.xz | |
soc/intel/icelake: lockdown: lock global reset
There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only
one (apollolake) is actually calling the code. Add the missing call.
Change-Id: I3e450a473ccdf99221e82e0f857879039d78991b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36572
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/icelake/lockdown.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/lockdown.c b/src/soc/intel/icelake/lockdown.c index 85a93c7c8e..b92d1c52f9 100644 --- a/src/soc/intel/icelake/lockdown.c +++ b/src/soc/intel/icelake/lockdown.c @@ -15,6 +15,7 @@ #include <device/mmio.h> #include <intelblocks/cfg.h> +#include <intelblocks/pmclib.h> #include <intelpch/lockdown.h> #include <soc/pm.h> @@ -60,6 +61,8 @@ static void pmc_lockdown_cfg(int chipset_lockdown) pmc_lock_pmsync(); /* Lock down ABASE and sleep stretching policy */ pmc_lock_abase(); + /* Make sure payload/OS can't trigger global reset */ + pmc_global_reset_disable_and_lock(); if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) pmc_lock_smi(); |