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authorMartin Roth <martinroth@chromium.org>2020-02-17 13:17:19 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-03-30 08:42:02 +0000
commit97bd2a7f33a784b63b8ede4efc23f39d4dfce37b (patch)
tree38d9cc42a61cfdc43ccd7f85d624a1f89d19ff0a /src/soc
parent91dddd47b3e5a34124e34222ab3f2a1f00ce9246 (diff)
downloadcoreboot-97bd2a7f33a784b63b8ede4efc23f39d4dfce37b.tar.xz
soc/amd/picasso: Add helper functions for finding SOC type
We're running into more and more situations where we need to tell one SOC type from another, and instead of rewriting them every time, just add some helper functions to the picasso SOC directory. Change-Id: I24b73145cdfa80c09fbe036d1fb6079696c6d013 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/2051514 Reviewed-on: https://chromium-review.googlesource.com/2060904 Reviewed-on: https://chromium-review.googlesource.com/2060905 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/picasso/Makefile.inc2
-rw-r--r--src/soc/amd/picasso/include/soc/soc_util.h8
-rw-r--r--src/soc/amd/picasso/soc_util.c33
3 files changed, 43 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index 48f65078ac..6b32c6e8e2 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -43,6 +43,7 @@ romstage-$(CONFIG_PICASSO_UART) += uart.c
romstage-y += tsc_freq.c
romstage-y += southbridge.c
romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
+romstage-y += soc_util.c
verstage-y += gpio.c
verstage-y += i2c.c
@@ -74,6 +75,7 @@ ramstage-$(CONFIG_PICASSO_UART) += uart.c
ramstage-y += usb.c
ramstage-y += tsc_freq.c
ramstage-y += finalize.c
+ramstage-y += soc_util.c
all-y += cfg_util.c
all-y += reset.c
diff --git a/src/soc/amd/picasso/include/soc/soc_util.h b/src/soc/amd/picasso/include/soc/soc_util.h
new file mode 100644
index 0000000000..be05d9f9af
--- /dev/null
+++ b/src/soc/amd/picasso/include/soc/soc_util.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+int soc_is_pollock(void);
+int soc_is_dali(void);
+int soc_is_picasso(void);
+int soc_is_raven2(void);
+int soc_is_zen_plus(void);
diff --git a/src/soc/amd/picasso/soc_util.c b/src/soc/amd/picasso/soc_util.c
new file mode 100644
index 0000000000..893ff2570f
--- /dev/null
+++ b/src/soc/amd/picasso/soc_util.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <arch/cpu.h>
+#include <soc/cpu.h>
+#include <soc/soc_util.h>
+
+int soc_is_pollock(void)
+{
+ return soc_is_zen_plus() && CONFIG(AMD_FT5);
+}
+
+int soc_is_dali(void)
+{
+ return soc_is_raven2() && CONFIG(AMD_FP5);
+}
+
+int soc_is_picasso(void)
+{
+ return soc_is_zen_plus() && CONFIG(AMD_FP5);
+}
+
+int soc_is_raven2(void)
+{
+ /* mask lower model number nibble and stepping */
+ return cpuid_eax(1) >> 8 == RAVEN2_CPUID >> 8;
+}
+
+int soc_is_zen_plus(void)
+{
+ /* mask lower model number nibble and stepping */
+ return cpuid_eax(1) >> 8 == PICASSO_CPUID >> 8;
+}