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| author | Aaron Durbin <adurbin@chromium.org> | 2016-01-22 15:43:43 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-02-04 17:35:16 +0100 |
| commit | a1faa4cfc7914af44f02278c68414a5aedc8ccf9 (patch) | |
| tree | d75d8013e27b84e8e4f825eea1b92e0dfc57d994 /src/soc | |
| parent | 49b2383ddb14f479cd2a5d1e01b1378810e8108e (diff) | |
| download | coreboot-a1faa4cfc7914af44f02278c68414a5aedc8ccf9.tar.xz | |
intel/skylake: implement vboot_platform_is_resuming()
To allow skylake platforms to run with verified memory init
code the chipset needs to implement vboot_platform_is_resuming()
so that the vboot code can make proper decisions.
BUG=chrome-os-partner:46049
BRANCH=glados
TEST=Suspended and resumed on chell. Also, tested with an EC build
which returns a bad hash to ensure that is properly caught.
Change-Id: I508a339c07dcc9e7c56a0df4201660827b3ae07a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a3e11789339bcd8fc8fc99b704c6a1110acf5302
Original-Change-Id: I40264019eb28e85795258112c720056a6a3fc523
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/323503
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13578
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/romstage/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/romstage/power_state.c | 7 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 00943bad38..194091f811 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,5 +1,6 @@ verstage-y += cpu.c verstage-y += pch.c +verstage-y += power_state.c verstage-y += report_platform.c verstage-y += romstage.c verstage-y += smbus.c diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c index d91e197711..cbef09a96c 100644 --- a/src/soc/intel/skylake/romstage/power_state.c +++ b/src/soc/intel/skylake/romstage/power_state.c @@ -30,6 +30,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> +#include <vendorcode/google/chromeos/vboot_common.h> static struct chipset_power_state power_state CAR_GLOBAL; @@ -151,3 +152,9 @@ struct chipset_power_state *fill_power_state(void) return ps; } + +int vboot_platform_is_resuming(void) +{ + int typ = (inl(ACPI_BASE_ADDRESS + PM1_CNT) & SLP_TYP) >> SLP_TYP_SHIFT; + return typ == SLP_TYP_S3; +} |