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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-05-25 10:28:11 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-29 20:06:04 +0000 |
| commit | a5eed800f3fa84ab100f7b612361c641515ee412 (patch) | |
| tree | 33a9d72dea2c7a2e8eb88b107824912176092afc /src/soc | |
| parent | 3d6ccd0489cfc973ba6a9a47b3e5567cd3a40acb (diff) | |
| download | coreboot-a5eed800f3fa84ab100f7b612361c641515ee412.tar.xz | |
soc/intel/common/cse: Don't use CAR_GLOBAL
All platforms using this code have NO_CAR_GLOBAL_MIGRATION.
Change-Id: If952ad8129e1fa6e45858cb77ec99c9fec55c4a6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/common/block/cse/cse.c | 22 |
1 files changed, 9 insertions, 13 deletions
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index e4fc6e4ff1..7bd46ceba9 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <arch/early_variables.h> #include <assert.h> #include <commonlib/helpers.h> #include <console/console.h> @@ -71,7 +70,7 @@ static struct cse_device { uintptr_t sec_bar; -} g_cse CAR_GLOBAL; +} g_cse; /* * Initialize the device with provided temporary BAR. If BAR is 0 use a @@ -80,7 +79,6 @@ static struct cse_device { */ void heci_init(uintptr_t tempbar) { - struct cse_device *cse = car_get_var_ptr(&g_cse); #if defined(__SIMPLE_DEVICE__) pci_devfn_t dev = PCH_DEV_CSE; #else @@ -89,7 +87,7 @@ void heci_init(uintptr_t tempbar) u8 pcireg; /* Assume it is already initialized, nothing else to do */ - if (cse->sec_bar) + if (g_cse.sec_bar) return; /* Use default pre-ram bar */ @@ -111,7 +109,7 @@ void heci_init(uintptr_t tempbar) pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config8(dev, PCI_COMMAND, pcireg); - cse->sec_bar = tempbar; + g_cse.sec_bar = tempbar; } /* Get HECI BAR 0 from PCI configuration space */ @@ -130,20 +128,18 @@ static uint32_t get_cse_bar(void) static uint32_t read_bar(uint32_t offset) { - struct cse_device *cse = car_get_var_ptr(&g_cse); /* Reach PCI config space to get BAR in case CAR global not available */ - if (!cse->sec_bar) - cse->sec_bar = get_cse_bar(); - return read32((void *)(cse->sec_bar + offset)); + if (!g_cse.sec_bar) + g_cse.sec_bar = get_cse_bar(); + return read32((void *)(g_cse.sec_bar + offset)); } static void write_bar(uint32_t offset, uint32_t val) { - struct cse_device *cse = car_get_var_ptr(&g_cse); /* Reach PCI config space to get BAR in case CAR global not available */ - if (!cse->sec_bar) - cse->sec_bar = get_cse_bar(); - return write32((void *)(cse->sec_bar + offset), val); + if (!g_cse.sec_bar) + g_cse.sec_bar = get_cse_bar(); + return write32((void *)(g_cse.sec_bar + offset), val); } static uint32_t read_cse_csr(void) |