diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-11-04 11:22:27 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-04-30 23:08:35 +0200 |
| commit | a90a59f5a3bfc22d6317186c004409469d1b031e (patch) | |
| tree | 13752bef4bbf93dba2681eaa25034bd474835a5f /src/soc | |
| parent | 81998090792ebc1a6e39455f5fcb4d2c9ec9c095 (diff) | |
| download | coreboot-a90a59f5a3bfc22d6317186c004409469d1b031e.tar.xz | |
baytrail: Fix XHCI problems and re-enable
- a few clock gating bits were set improperly and were preventing
the system from transitioning out of S0 state.
- the XHCC registers were not getting the top byte set properly
which includes things like DMA write request size and request
boundary crossing control. This was causing memory corruption.
BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=build and boot kernel from USB on rambi with XHCI driver
Change-Id: I8e8135a793dfbaa1f163766702e3a8f19bba9703
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175558
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4933
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/baytrail/xhci.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index 244a4dcec7..30e60981e9 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -83,11 +83,11 @@ const struct reg_script xhci_init_script[] = { /* BAR + 0x0010[10,9,5]=110b */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x0010, ~0x00000020, 0x00000600), /* BAR + 0x8058[20,16,8]=110b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8058, ~0x00000010, 0x00110000), + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8058, ~0x00000100, 0x00110000), /* BAR + 0x8060[25]=1b */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8060, 0x02000000), - /* BAR + 0x80e0[19,9,6]=001b, toggle bit 24=1 */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x00010020, 0x01000040), + /* BAR + 0x80e0[16,9,6]=001b, toggle bit 24=1 */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x00010200, 0x01000040), /* BAR + 0x80e0 toggle bit 24=0 */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01000000, 0), /* BAR + 0x80f0[20]=0b */ @@ -113,7 +113,7 @@ const struct reg_script xhci_init_script[] = { const struct reg_script xhci_clock_gating_script[] = { /* ConfigureXhciClockGating() */ /* D20:F0:40[21:19,18,10:8]=000,1,001 (don't write byte 3) */ - REG_PCI_RMW16(0x40, ~0x0300, 0x0010), + REG_PCI_RMW16(0x40, ~0x0600, 0x0100), REG_PCI_RMW8(0x42, ~0x38, 0x04), /* D20:F0:44[5:3]=001b */ REG_PCI_RMW16(0x44, ~0x0030, 0x0008), @@ -187,6 +187,9 @@ static void xhci_init(device_t dev) REG_SCRIPT_NEXT(xhci_init_script), /* Initialize clock gating */ REG_SCRIPT_NEXT(xhci_clock_gating_script), + /* Finalize XHCC1 and XHCC2 */ + REG_PCI_RMW32(0x44, ~0x00000000, 0x83c00000), + REG_PCI_RMW32(0x40, ~0x00800000, 0x80000000), /* Set USB2 Port Routing Mask */ REG_PCI_WRITE32(XHCI_USB2PRM, BYTM_USB2_PORT_MAP), /* Set USB3 Port Routing Mask */ |