summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2020-10-28 18:24:56 +0100
committerArthur Heymans <arthur@aheymans.xyz>2020-11-04 08:27:31 +0000
commitb38d6bbe1c74309f078915c2d467475bb4144943 (patch)
tree619b08c414989adbc5af31a63a803f7b17cda0ba /src/soc
parent3cea0594df500c2f08448ea4e5383fab63a7ab77 (diff)
downloadcoreboot-b38d6bbe1c74309f078915c2d467475bb4144943.tar.xz
soc/intel/xeon_sp/cpx: Align coreboot CAR symbols to FSP-T
The CAR set up by FSP-T is at base 0xfe800000 and has a 0x200000 size. FSP-M seems to have a very large stack usage so it would overflow other car symbols located below the coreboot stack such as timestamps and the pre-ram console, which are now fixed. TEST: boot with ocp/deltalake. Change-Id: I886f9391ad79fcfa0724109393e3781a08d954b4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46895 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/xeon_sp/cpx/Kconfig19
1 files changed, 12 insertions, 7 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
index 975afc9e26..28e7b83386 100644
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -27,22 +27,25 @@ config PCR_BASE_ADDRESS
config DCACHE_RAM_BASE
hex
- default 0xfe8b0000
+ default 0xfe800000
config DCACHE_RAM_SIZE
hex
- default 0x170000
+ default 0x1fff00
help
The size of the cache-as-ram region required during bootblock
- and/or romstage.
+ and/or romstage. FSP-T reserves the upper 0x100 for
+ FspReservedBuffer.
config DCACHE_BSP_STACK_SIZE
hex
- default 0xA0000
+ default 0x140000
help
The amount of anticipated stack usage in CAR by bootblock and
other stages. It needs to include FSP-M stack requirement and
- CB romstage stack requirement.
+ CB romstage stack requirement. The integration documentation
+ says this needs to be 256KiB, but practice show this needs to
+ be a lot more.
config CPU_MICROCODE_CBFS_LOC
hex
@@ -67,11 +70,13 @@ config STACK_SIZE
config FSP_TEMP_RAM_SIZE
hex
depends on FSP_USES_CB_STACK
- default 0xA0000
+ default 0x40000
help
The amount of anticipated heap usage in CAR by FSP.
Refer to Platform FSP integration guide document to know
- the exact FSP requirement for Heap setup.
+ the exact FSP requirement for Heap setup. The FSP integration
+ documentation says this needs to be at least 128KiB, but practice
+ show this needs to be 256KiB or more.
config SOC_INTEL_COMMON_BLOCK_P2SB
def_bool y