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authorDuncan Laurie <dlaurie@chromium.org>2013-12-04 18:34:11 -0800
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-05-08 07:06:07 +0200
commitb50566ef63b560ed149db6aeb19004d7c0345275 (patch)
tree31221c6af6cdad6ce31014540e8e5a074a4305dd /src/soc
parentac9a905cf1e44570a27dea0afd9233b7418d9c1e (diff)
downloadcoreboot-b50566ef63b560ed149db6aeb19004d7c0345275.tar.xz
baytrail: Fix _CRS to build with new IASL
The new IASL is complaining about the PCI memory region not having consistent base/end/length values because they are placeholder that are fixed up in the method before returning. Put in some more valid placeholder values to make it happy. BUG=chromium:311294 BRANCH=none TEST=build and boot with IASL 20130117 on rambi Change-Id: I0e21adcce43deb14d3c2c45787ff8c9efc357c2f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178864 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Duncan Laurie <dlaurie@google.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4988 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/baytrail/acpi/southcluster.asl4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl
index 1bc7eba650..49349c4649 100644
--- a/src/soc/intel/baytrail/acpi/southcluster.asl
+++ b/src/soc/intel/baytrail/acpi/southcluster.asl
@@ -160,8 +160,8 @@ Method (_CRS, 0, Serialized)
// PCI Memory Region (Top of memory-0xfeafffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
- 0x00000000, 0x00000000, 0xfeafffff, 0x00000000,
- 0xfeb00000,,, PMEM)
+ 0x00000000, 0xfea00000, 0xfeafffff, 0x00000000,
+ 0x00100000,,, PMEM)
// TPM Area (0xfed40000-0xfed44fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,