summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorMatt DeVillier <matt.devillier@gmail.com>2017-04-17 18:36:26 -0500
committerMartin Roth <martinroth@google.com>2017-06-04 21:38:48 +0200
commitb79d058767f782718d757c41377132de573aac4c (patch)
tree68a503a8a1df22bc5d5700c0bc720b624c48e812 /src/soc
parentce768f3baff20815f227fffbf1bb406f3a7dd1a7 (diff)
downloadcoreboot-b79d058767f782718d757c41377132de573aac4c.tar.xz
soc/broadwell: add ACPI method to generate USB port info
Add ACPI method GPLD to generate port location data when passed visiblity info. Will be used by _PLD method in board-specific USB .asl files. Change-Id: Id6e6699fe3eaafbe6847479d45c70a1d57bd327a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/broadwell/acpi/xhci.asl16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/acpi/xhci.asl b/src/soc/intel/broadwell/acpi/xhci.asl
index 53b3956908..d638a27d30 100644
--- a/src/soc/intel/broadwell/acpi/xhci.asl
+++ b/src/soc/intel/broadwell/acpi/xhci.asl
@@ -355,6 +355,22 @@ Device (XHCI)
{
Name (_ADR, 0x00000000)
+ // GPLD: Generate Port Location Data (PLD)
+ Method (GPLD, 1, Serialized) {
+ Name (PCKG, Package (0x01) {
+ Buffer (0x10) {}
+ })
+
+ // REV: Revision 0x02 for ACPI 5.0
+ CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV)
+ Store (0x02, REV)
+
+ // VISI: Port visibility to user per port
+ CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI)
+ Store (Arg0, VISI)
+ Return (PCKG)
+ }
+
Device (PRT1) { Name (_ADR, 1) } // USB Port 0
Device (PRT2) { Name (_ADR, 2) } // USB Port 1
Device (PRT3) { Name (_ADR, 3) } // USB Port 2