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author | Youness Alaoui <youness.alaoui@puri.sm> | 2017-05-03 17:57:13 -0400 |
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committer | Martin Roth <martinroth@google.com> | 2017-06-09 16:59:30 +0200 |
commit | bb5fb64e11aa7eb6534a5dd5a06d5ea29dc4d411 (patch) | |
tree | c298d9acae216d54ecb283b8380ca03570a0b239 /src/soc | |
parent | 3c0d7d21efd739101658069683b08c5aab320837 (diff) | |
download | coreboot-bb5fb64e11aa7eb6534a5dd5a06d5ea29dc4d411.tar.xz |
pciexp_device: Prevent race condition with retrain link
The PCIe specification[1] describes a race condition that
can occur when using the Retrain Link bit in the Link
Control Register.
The race condition is avoided by checking the retrain link
bit in the link status register and waiting until it is
set to 0, before initiating a new link retraining.
[1] PCI Express Base Specification Revision 3.0
Page 633
Change-Id: I9d5840fb9a6e63838b5a4084d3bbe483f1d870ed
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/19556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc')
0 files changed, 0 insertions, 0 deletions