diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2016-10-28 09:07:49 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2016-10-28 18:59:46 +0200 |
| commit | c806e4cc59208afb8b00da0a2cd34909e6bb9fb3 (patch) | |
| tree | 417425ad4b9b2269da0032804ed2d7b00c903bf7 /src/soc | |
| parent | ffddf7beb455759e3d3962475deca52b88b19d5a (diff) | |
| download | coreboot-c806e4cc59208afb8b00da0a2cd34909e6bb9fb3.tar.xz | |
skylake: Add GPIO macro for configuring inverted APIC input
Add a GPIO macro that allows a pin to be routed to the APIC with
the input inverted. This allows a normal interrupt to get used as
a GPE during firmware and still be used as a perhiperal interrupt
in the kernel.
BUG=chrome-os-partner:58666
TEST=boot en eve and use TPM IRQ in firmware and OS
Change-Id: I77f727f749fdd5281ff595a9237fe1e634daba96
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17176
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/gpio.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index d86af0f54a..dd9b9a340c 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -144,6 +144,12 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num); _PAD_CFG(pad_, term_, \ _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, YES, NO, NO, NO, GPIO, NO, YES)) +/* General purpose input passed through to IOxAPIC as inverted input. */ +#define PAD_CFG_GPI_APIC_INVERT(pad_, term_, rst_) \ + _PAD_CFG(pad_, term_, \ + _DW0_VALS(rst_, RAW, NO, LEVEL, NO, YES, YES, NO, NO, NO, GPIO, NO, \ + YES)) + /* General purpose input routed to SCI. This assumes edge triggered events. */ #define PAD_CFG_GPI_ACPI_SCI(pad_, term_, rst_, inv_) \ _PAD_CFG_ATTRS(pad_, term_, \ |