diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-07-13 12:51:19 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-27 21:18:45 +0000 |
| commit | c95d6ffa7cd532243210723e43b977aa880a72e8 (patch) | |
| tree | 8d99fcd937b9389a936899ce595fa0f28df6b922 /src/soc | |
| parent | 7bf860ffedb10a5d69381ad92b3eb7a1169969a9 (diff) | |
| download | coreboot-c95d6ffa7cd532243210723e43b977aa880a72e8.tar.xz | |
soc/amd/stoneyridge: Convert 48Mhz enable to read/write32
Use the appropriate read32() and write32() calls. Remove unnecessary
cast.
Change-Id: Ib5430bdb30844d3508a09ddb77a969c0628f6c7d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/stoneyridge/early_setup.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c index ca3447f6a7..f1539eae52 100644 --- a/src/soc/amd/stoneyridge/early_setup.c +++ b/src/soc/amd/stoneyridge/early_setup.c @@ -224,18 +224,17 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) void hudson_clk_output_48Mhz(void) { - u32 data, *memptr; + u32 ctrl; /* * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so * 48Mhz will be on ball AP13 (FT3b package) */ - memptr = (u32 *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40); - data = *memptr; + ctrl = read32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40)); /* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */ - data &= (u32)~(1<<2); - *memptr = data; + ctrl &= ~(1<<2); + write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl); } static uintptr_t hudson_spibase(void) |