summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorDuncan Laurie <dlaurie@chromium.org>2014-12-10 09:13:38 -0800
committerMarc Jones <marc.jones@se-eng.com>2015-04-15 21:45:54 +0200
commitcb12f65931aa0bbc30c0e578c988452be70714ed (patch)
tree12eb87c66ecd2b9a7200e3219ef194ecb4383ab6 /src/soc
parentc99681f4f23ddacd64fddbedf060f6443d008090 (diff)
downloadcoreboot-cb12f65931aa0bbc30c0e578c988452be70714ed.tar.xz
broadwell: Remove unused bootblock code
This code that stores the initial timestamp is not being used, instead the timestamp is passed to romstage_main(). BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Original-Change-Id: I0e0fa1ba74ab93d4454fdfa12208e712d2ae913c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234402 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit 838112cf79e2b4d51e5dc87d5ac9cd7e03807f29) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8fd7ba72c14c1e39f7bfa3a1ae8d03289a2abf73 Reviewed-on: http://review.coreboot.org/9698 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/broadwell/bootblock/pch.c15
1 files changed, 0 insertions, 15 deletions
diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c
index 0115719837..2fa722097c 100644
--- a/src/soc/intel/broadwell/bootblock/pch.c
+++ b/src/soc/intel/broadwell/bootblock/pch.c
@@ -18,24 +18,12 @@
*/
#include <arch/io.h>
-#include <cpu/x86/tsc.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
#include <soc/pci_devs.h>
#include <soc/rcba.h>
#include <soc/spi.h>
-static void store_initial_timestamp(void)
-{
- /* Two 32bit scratchpad registers available:
- * D0:F0 0xdc (SKPAD)
- * D31:F2 0xd0 (SATA SP)
- */
- tsc_t tsc = rdtsc();
- pci_write_config32(SA_DEV_ROOT, 0xdc, tsc.lo);
- pci_write_config32(PCH_DEV_SATA, 0xd0, tsc.hi);
-}
-
/*
* Enable Prefetching and Caching.
*/
@@ -84,9 +72,6 @@ static void set_spi_speed(void)
static void bootblock_southbridge_init(void)
{
-#if CONFIG_COLLECT_TIMESTAMPS
- store_initial_timestamp();
-#endif
map_rcba();
enable_spi_prefetch();
enable_port80_on_lpc();