soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size()

This change uses cpu_phys_address_size() to calculate the size of high
MMIO region instead of a macro for each SoC. This ensures that the
entire range above TOUUD that can be addressed by the CPU is used for
MMIO above 4G boundary.

Change-Id: I01a1a86c0c65856f9f35185c2f233c58f18f5dfe
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

7 files changed, 3 insertions, 15 deletions

diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h
index e79331a3e8..5e5b40e2e1 100644
--- a/src/soc/intel/apollolake/include/soc/iomap.h
+++ b/src/soc/intel/apollolake/include/soc/iomap.h
@@ -45,6 +45,4 @@
 #define EARLY_I2C_BASE_ADDRESS		0xfe020000
 #define EARLY_I2C_BASE(x)	(EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
 
-#define ABOVE_4GB_MEM_BASE_SIZE	(64ULL * GiB)
-
 #endif /* _SOC_APOLLOLAKE_IOMAP_H_ */
diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h
index 9d13d84d3a..dc070893c8 100644
--- a/src/soc/intel/cannonlake/include/soc/iomap.h
+++ b/src/soc/intel/cannonlake/include/soc/iomap.h
@@ -54,8 +54,6 @@
 
 #define HECI1_BASE_ADDRESS	0xfeda2000
 
-#define ABOVE_4GB_MEM_BASE_SIZE	(256ULL * GiB)
-
 /* PTT registers */
 #define PTT_TXT_BASE_ADDRESS	0xfed30800
 #define PTT_PRESENT		0x00070000
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 7355817ec2..269236ba32 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -2,6 +2,7 @@
 
 #include <cbmem.h>
 #include <console/console.h>
+#include <cpu/cpu.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
@@ -102,8 +103,8 @@ void sa_fill_gnvs(global_nvs_t *gnvs)
 	struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 
 	sa_read_map_entry(sa_dev, &sa_memory_map[SA_TOUUD_REG], &gnvs->a4gb);
-	gnvs->a4gs = ABOVE_4GB_MEM_BASE_SIZE;
-	printk(BIOS_DEBUG, "PCI space above 4GB MMIO is from 0x%llx  to len = 0x%llx\n",
+	gnvs->a4gs = POWER_OF_2(cpu_phys_address_size()) - gnvs->a4gb;
+	printk(BIOS_DEBUG, "PCI space above 4GB MMIO is at 0x%llx, len = 0x%llx\n",
 	       gnvs->a4gb, gnvs->a4gs);
 }
 
diff --git a/src/soc/intel/icelake/include/soc/iomap.h b/src/soc/intel/icelake/include/soc/iomap.h
index 6971a3d564..6b82c19ae2 100644
--- a/src/soc/intel/icelake/include/soc/iomap.h
+++ b/src/soc/intel/icelake/include/soc/iomap.h
@@ -48,8 +48,6 @@
 #define VTD_BASE_ADDRESS	0xFED90000
 #define VTD_BASE_SIZE		0x00004000
 
-#define ABOVE_4GB_MEM_BASE_SIZE	(256ULL * GiB)
-
 /*
  * I/O port address space
  */
diff --git a/src/soc/intel/jasperlake/include/soc/iomap.h b/src/soc/intel/jasperlake/include/soc/iomap.h
index 3ee06a2d2f..c45430a02e 100644
--- a/src/soc/intel/jasperlake/include/soc/iomap.h
+++ b/src/soc/intel/jasperlake/include/soc/iomap.h
@@ -70,8 +70,6 @@
 #define VTD_BASE_ADDRESS	0xfed90000
 #define VTD_BASE_SIZE		0x00004000
 
-#define ABOVE_4GB_MEM_BASE_SIZE	(256ULL * GiB)
-
 #define MCH_BASE_ADDRESS	0xfea80000
 #define MCH_BASE_SIZE		0x8000
 
diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h
index a3db5c033e..d3fb9579fd 100644
--- a/src/soc/intel/skylake/include/soc/iomap.h
+++ b/src/soc/intel/skylake/include/soc/iomap.h
@@ -61,8 +61,6 @@
 #define PTT_TXT_BASE_ADDRESS	0xfed30800
 #define PTT_PRESENT		0x00070000
 
-#define ABOVE_4GB_MEM_BASE_SIZE	(64ULL * GiB)
-
 /*
  * I/O port address space
  */
diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h
index 70f908d57d..282092fade 100644
--- a/src/soc/intel/tigerlake/include/soc/iomap.h
+++ b/src/soc/intel/tigerlake/include/soc/iomap.h
@@ -76,9 +76,6 @@
 #define VTD_BASE_ADDRESS	0xfed90000
 #define VTD_BASE_SIZE		0x00004000
 
-#define ABOVE_4GB_MEM_BASE_SIZE	(256ULL * GiB)
-
-
 #define MCH_BASE_ADDRESS	0xfedc0000
 #define MCH_BASE_SIZE		0x20000