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authorAndrey Petrov <andrey.petrov@intel.com>2016-04-21 14:53:33 -0700
committerAaron Durbin <adurbin@chromium.org>2016-04-28 05:10:53 +0200
commitd047ab590e525ae72aea117953250b25f71a1e60 (patch)
tree644d2b9d4c37da0cccdd01b4c4f233daf87f553a /src/soc
parent4005d9b2e42d6d8e70e9fb4b88002b3a69d20bca (diff)
downloadcoreboot-d047ab590e525ae72aea117953250b25f71a1e60.tar.xz
soc/intel/apollolake: Actually include ACPI PCI IRQ definitions
Without ACPI PCI IRQ definitions kernel is left only with informaiton available in PCI config space, which is not sufficient. Change-Id: I3854781049851b5aa5b2dbf3257ece2fee76c3e2 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14465 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/apollolake/acpi/soc_int.asl1
-rw-r--r--src/soc/intel/apollolake/acpi/southbridge.asl3
2 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/acpi/soc_int.asl b/src/soc/intel/apollolake/acpi/soc_int.asl
index 83a831fcd2..7db23ee0d7 100644
--- a/src/soc/intel/apollolake/acpi/soc_int.asl
+++ b/src/soc/intel/apollolake/acpi/soc_int.asl
@@ -51,6 +51,7 @@
#define SPI2_INT 37
#define UFS_INT 38
#define EMMC_INT 39
+#define PMC_INT 40
#define SDIO_INT 42
#endif /* _SOC_INT_DEFINE_ASL_ */
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index cc526763c6..46d701328a 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -17,3 +17,6 @@
/* LPSS device */
#include "lpss.asl"
+
+/* PCI IRQ assignment */
+#include "pci_irqs.asl"