summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorFurquan Shaikh <furquan@google.com>2020-06-10 15:35:44 -0700
committerFurquan Shaikh <furquan@google.com>2020-06-12 02:16:57 +0000
commitd5f1e0f9734273f79ebd313bb6a17eda04c22c11 (patch)
tree3bc7db5b4598e575793958054310cf0803d43e29 /src/soc
parent6740647cfd2d8ff8840d1e2ab37b66ce14b19180 (diff)
downloadcoreboot-d5f1e0f9734273f79ebd313bb6a17eda04c22c11.tar.xz
soc/amd/picasso: Reconfigure SPI speeds after FSP-S has run
This change reconfigures SPI speeds after FSP-S has run since FSP-S is currently configuring the SPI frequency when it should not. Until FSP-S behavior is fixed, this workaround needs to be applied. BUG=b:153506142 TEST=Verified that em100 works fine. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Id9b8330c6f82c7162ff91e8cc10160fdd8cfedab Reviewed-on: https://review.coreboot.org/c/coreboot/+/42267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/picasso/chip.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c
index 2e5fae58e5..f703a0f7de 100644
--- a/src/soc/amd/picasso/chip.c
+++ b/src/soc/amd/picasso/chip.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <amdblocks/spi.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@@ -164,6 +165,13 @@ static void soc_init(void *chip_info)
fsp_silicon_init(acpi_is_wakeup_s3());
+ /*
+ * TODO(furquan): Get rid of this once FSP is fixed to not touch SPI
+ * registers(b/153506142). Currently, FSP-S reconfigures SPI frequency causing em100 to
+ * stop working. Thus, reconfigure SPI speeds here.
+ */
+ fch_spi_config_modes();
+
data_fabric_set_mmio_np();
southbridge_init(chip_info);
}