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authorDuncan Laurie <dlaurie@chromium.org>2014-08-26 13:47:18 -0700
committerMarc Jones <marc.jones@se-eng.com>2015-03-27 06:24:20 +0100
commitedb55fc0ad232b666684977ba4f0fece4a858ffb (patch)
tree0458a7dc7e26d760d414b55148a3b7a06ad36190 /src/soc
parent55228ba4b41e820efea71a75c649a6dd29cc76d5 (diff)
downloadcoreboot-edb55fc0ad232b666684977ba4f0fece4a858ffb.tar.xz
broadwell: Fix GPE register addresses
This macro is incorrect and should be counting by dword instead of byte. The effects of this were subtle: incorrect events in ELOG and hanging when waking from USB input because PME_B0 was not disabled properly. BUG=chrome-os-partner:31611 BRANCH=none TEST=test wake from suspend with USB keyboard Original-Change-Id: I7caf1d46283071787550a9765703897181774957 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214258 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3cfc4a1812466cb1c1317b8f21321aafee623857) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I3e2f8190d824692ecb961615becf65319a6ffd8b Reviewed-on: http://review.coreboot.org/8965 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/broadwell/broadwell/pm.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/broadwell/broadwell/pm.h b/src/soc/intel/broadwell/broadwell/pm.h
index 91f55fe1fb..886e1001f7 100644
--- a/src/soc/intel/broadwell/broadwell/pm.h
+++ b/src/soc/intel/broadwell/broadwell/pm.h
@@ -83,11 +83,11 @@
#define TCO2_STS 0x66
#define TCO2_STS_SECOND_TO (1 << 1)
-#define GPE0_STS(x) (0x80 + x)
+#define GPE0_STS(x) (0x80 + (x * 4))
#define GPE_31_0 0 /* 0x80/0x90 = GPE[31:0] */
-#define GPE_63_32 1 /* 0x80/0x90 = GPE[63:32] */
-#define GPE_94_64 2 /* 0x80/0x90 = GPE[94:64] */
-#define GPE_STD 3 /* 0x80/0x90 = Standard GPE */
+#define GPE_63_32 1 /* 0x84/0x94 = GPE[63:32] */
+#define GPE_94_64 2 /* 0x88/0x98 = GPE[94:64] */
+#define GPE_STD 3 /* 0x8c/0x9c = Standard GPE */
#define WADT_STS (1 << 18)
#define GP27_STS (1 << 16)
#define PME_B0_STS (1 << 13)
@@ -99,7 +99,7 @@
#define TCOSCI_STS (1 << 6)
#define SWGPE_STS (1 << 2)
#define HOT_PLUG_STS (1 << 1)
-#define GPE0_EN(x) (0x90 + x)
+#define GPE0_EN(x) (0x90 + (x * 4))
#define WADT_en (1 << 18)
#define GP27_EN (1 << 16)
#define PME_B0_EN (1 << 13)