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| author | Shaunak Saha <shaunak.saha@intel.com> | 2018-08-31 12:49:08 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-09-10 15:02:05 +0000 |
| commit | ef250c47e4726c2648c96d1d06f7da45b221c359 (patch) | |
| tree | 4cc7f632ca21bc5783f86040cf8224eb56c1b6ba /src/soc | |
| parent | f47ccbdd47c57def602201869081d1025014c042 (diff) | |
| download | coreboot-ef250c47e4726c2648c96d1d06f7da45b221c359.tar.xz | |
soc/intel/skylake: Add support for CmdTriStateDis UPD in devicetree
This patch adds the support for CmdTriStateDis FSP upd in skylake
soc structure so that we can define it in devicetree.CmdTriStateDis
needed to be set for the skylake/kabylake based boards where LPDDR3
design is without RTT for CMD/CTRL.We need to set this bit for those
designs for the margin to be proper.
BUG=b:111812662
TEST=Run memtester app and also webgl fishtank on
the LPDDR3 kabylake boards and also check the
margin data is proper in FSP.
Change-Id: Ida69e443aa6ea4b524bd3ea2dcf26f4e63010291
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/28424
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage_fsp20.c | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index ec8b461647..5bf39318bb 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -154,6 +154,9 @@ struct soc_intel_skylake_config { /* Enable/disable Rank Margin Tool */ u8 Rmt; + /* Disable Command TriState */ + u8 CmdTriStateDis; + /* Lan */ u8 EnableLan; u8 EnableLanLtr; diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 64f9d7d2be..45fb2d0ef3 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -224,6 +224,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->SaGv = config->SaGv; m_cfg->UserBd = BOARD_TYPE_ULT_ULX; m_cfg->RMT = config->Rmt; + m_cfg->CmdTriStateDis = config->CmdTriStateDis; m_cfg->DdrFreqLimit = config->DdrFreqLimit; m_cfg->VmxEnable = config->VmxEnable; m_cfg->PrmrrSize = config->PrmrrSize; |