ipq8064: Make timer code compile

Commment out nonessential timer services and modify the source code to
cleanly build in coeboot environment. Do not remove dead code just
yet, these functions might be necessary later.

Need to rename the soc timer.h to prevent collisions with timer.h in
the top level include directory.

Currently build timer code for ramstage only.

BUG=chrome-os-partner:27784
TEST='emerge-storm coreboot' still succeeds

Original-Change-Id: Ib10133ccb42697840708845a8ea6d75ceeaeb3d5
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/194067
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 987ce95220953c16216d1e1d70d5a941d05fc9bc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ia9cf175da11c70709354def5e51bf79df4fda2fe
Reviewed-on: http://review.coreboot.org/7269
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>

6 files changed, 53 insertions, 47 deletions

diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc
index 8432e5e090..904251102d 100644
--- a/src/soc/qualcomm/ipq806x/Makefile.inc
+++ b/src/soc/qualcomm/ipq806x/Makefile.inc
@@ -6,6 +6,7 @@ romstage-y += gpio.c
 
 ramstage-y += cbfs.c
 ramstage-y += gpio.c
+ramstage-y += timer.c
 
 ifeq ($(CONFIG_USE_BLOBS),y)
 
diff --git a/src/soc/qualcomm/ipq806x/cbfs.c b/src/soc/qualcomm/ipq806x/cbfs.c
index eec9b7353b..97ae548821 100644
--- a/src/soc/qualcomm/ipq806x/cbfs.c
+++ b/src/soc/qualcomm/ipq806x/cbfs.c
@@ -24,12 +24,3 @@ int init_default_cbfs_media(struct cbfs_media *media)
 {
 	return 0;
 }
-
-/*
- * Temporary change to make sure storm code still builds. Will be dropped
- * shortly.
- */
-#include <delay.h>  /* This driver serves as a CBFS media source. */
-void init_timer(void)
-{
-}
diff --git a/src/soc/qualcomm/ipq806x/include/cdp.h b/src/soc/qualcomm/ipq806x/include/cdp.h
index 4ae476a278..22ba192bc4 100644
--- a/src/soc/qualcomm/ipq806x/include/cdp.h
+++ b/src/soc/qualcomm/ipq806x/include/cdp.h
@@ -4,9 +4,23 @@
 #ifndef  _IPQ806X_CDP_H_
 #define  _IPQ806X_CDP_H_
 
-#include <phy.h>
+unsigned smem_get_board_machtype(void);
 
-unsigned int smem_get_board_machtype(void);
+typedef enum {
+        PHY_INTERFACE_MODE_MII,
+        PHY_INTERFACE_MODE_GMII,
+        PHY_INTERFACE_MODE_SGMII,
+        PHY_INTERFACE_MODE_QSGMII,
+        PHY_INTERFACE_MODE_TBI,
+        PHY_INTERFACE_MODE_RMII,
+        PHY_INTERFACE_MODE_RGMII,
+        PHY_INTERFACE_MODE_RGMII_ID,
+        PHY_INTERFACE_MODE_RGMII_RXID,
+        PHY_INTERFACE_MODE_RGMII_TXID,
+        PHY_INTERFACE_MODE_RTBI,
+        PHY_INTERFACE_MODE_XGMII,
+        PHY_INTERFACE_MODE_NONE /* Must be last */
+} phy_interface_t;
 
 typedef struct {
 	unsigned int gpio;
@@ -73,17 +87,17 @@ typedef struct {
 } spinorflash_params_t;
 
 typedef struct {
-	uint count;
-	u8 addr[7];
+	unsigned count;
+	uint8_t addr[7];
 } ipq_gmac_phy_addr_t;
 
 typedef struct {
-	uint base;
+	unsigned base;
 	int unit;
-	uint is_macsec;
-	uint mac_pwr0;
-	uint mac_pwr1;
-	uint mac_conn_to_phy;
+	unsigned is_macsec;
+	unsigned mac_pwr0;
+	unsigned mac_pwr1;
+	unsigned mac_conn_to_phy;
 	phy_interface_t phy;
 	ipq_gmac_phy_addr_t phy_addr;
 } ipq_gmac_board_cfg_t;
@@ -98,6 +112,7 @@ typedef struct {
 	unsigned int uart_gsbi_base;
 	unsigned int uart_dm_base;
 	unsigned int clk_dummy;
+#if 0
 	uart_clk_mnd_t mnd_value;
 	unsigned int gmac_gpio_count;
 	gpio_func_data_t *gmac_gpio;
@@ -105,10 +120,12 @@ typedef struct {
 	flash_desc flashdesc;
 	spinorflash_params_t flash_param;
 	gpio_func_data_t dbg_uart_gpio[NO_OF_DBG_UART_GPIOS];
+#endif
 } __attribute__ ((__packed__)) board_ipq806x_params_t;
 
 extern board_ipq806x_params_t *gboard_param;
 
+#if 0
 static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg)
 {
 	/*
@@ -121,7 +138,8 @@ static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg)
 		(cfg < &gboard_param->gmac_cfg[IPQ_GMAC_NMACS]) &&
 		(cfg->unit >= 0) && (cfg->unit < IPQ_GMAC_NMACS));
 }
+#endif
 
-unsigned int get_board_index(unsigned int machid);
-void ipq_configure_gpio(gpio_func_data_t *gpio, uint count);
+unsigned int get_board_index(unsigned machid);
+void ipq_configure_gpio(gpio_func_data_t *gpio, unsigned count);
 #endif
diff --git a/src/soc/qualcomm/ipq806x/include/iomap.h b/src/soc/qualcomm/ipq806x/include/iomap.h
index 5fcfde9ee7..8642410616 100644
--- a/src/soc/qualcomm/ipq806x/include/iomap.h
+++ b/src/soc/qualcomm/ipq806x/include/iomap.h
@@ -43,6 +43,8 @@
  */
 #define readl_i(a)           read32((const void *)(a))
 #define writel_i(v,a)        write32(v,(void *)a)
+#include <arch/io.h>
+#include <cdp.h>
 
 #define MSM_CLK_CTL_BASE    0x00900000
 
@@ -50,7 +52,7 @@
 #define MSM_GPT_BASE        (MSM_TMR_BASE + 0x04)
 #define MSM_DGT_BASE        (MSM_TMR_BASE + 0x24)
 
-#define GPT_REG(off)        (MSM_GPT_BASE + (off))
+#define GPT_REG(off)        (((uint8_t *)(MSM_GPT_BASE)) + (off))
 #define DGT_REG(off)        (MSM_DGT_BASE + (off))
 
 #define APCS_WDT0_EN        (MSM_TMR_BASE + 0x0040)
diff --git a/src/soc/qualcomm/ipq806x/include/timer.h b/src/soc/qualcomm/ipq806x/include/ipq_timer.h
index 4e1ef34294..4e1ef34294 100644
--- a/src/soc/qualcomm/ipq806x/include/timer.h
+++ b/src/soc/qualcomm/ipq806x/include/ipq_timer.h
diff --git a/src/soc/qualcomm/ipq806x/timer.c b/src/soc/qualcomm/ipq806x/timer.c
index 691ccbd2c5..5c0dcb24bf 100644
--- a/src/soc/qualcomm/ipq806x/timer.c
+++ b/src/soc/qualcomm/ipq806x/timer.c
@@ -31,14 +31,10 @@
  * SUCH DAMAGE.
  */
 
-#include <asm/arch-ipq806x/iomap.h>
-#include <asm/io.h>
-#include <common.h>
-#include <asm/types.h>
-#include <asm/arch-ipq806x/timer.h>
-
-static ulong timestamp;
-static ulong lastinc;
+#include <delay.h>
+#include <iomap.h>
+#include <ipq_timer.h>
+#include <timer.h>
 
 #define GPT_FREQ_KHZ    32
 #define GPT_FREQ	(GPT_FREQ_KHZ * 1000)	/* 32 KHz */
@@ -46,36 +42,24 @@ static ulong lastinc;
 /**
  * timer_init - initialize timer
  */
-int timer_init(void)
+void init_timer(void)
 {
 	writel(0, GPT_ENABLE);
 	writel(GPT_ENABLE_EN, GPT_ENABLE);
-	return 0;
-}
-
-/**
- * get_timer - returns time lapsed
- * @base: base/start time
- *
- * Returns time lapsed, since the specified base time value.
- */
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
 }
 
 /**
- * __udelay -  generates micro second delay.
+ * udelay -  generates micro second delay.
  * @usec: delay duration in microseconds
  *
  * With 32KHz clock, minimum possible delay is 31.25 Micro seconds and
  * its multiples. In Rumi GPT clock is 32 KHz
  */
-void __udelay(unsigned long usec)
+void udelay(unsigned usec)
 {
-	unsigned int val;
-	ulong now, last;
-	ulong runcount;
+	unsigned val;
+	unsigned now, last;
+	unsigned runcount;
 
 	usec = (usec + GPT_FREQ_KHZ - 1) / GPT_FREQ_KHZ;
 	last = readl(GPT_COUNT_VAL);
@@ -92,6 +76,15 @@ void __udelay(unsigned long usec)
 	} while (runcount < val);
 }
 
+#if 0
+
+/*
+ * TODO(vbendeb) clean it up later.
+ * Compile out the below code but leave it for now in case it will become
+ * necessary later in order to make the platform fully functional.
+ */
+static unsigned long timestamp;
+static unsigned long lastinc;
 
 inline ulong gpt_to_sys_freq(unsigned int gpt)
 {
@@ -137,3 +130,4 @@ ulong get_tbclk(void)
 {
         return GPT_FREQ;
 }
+#endif