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authorBrandon Breitenstein <brandon.breitenstein@intel.com>2020-03-11 14:07:23 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-03-30 08:40:45 +0000
commitfc932374a2860addbdf00dc3bd141b556508b8f3 (patch)
tree3baf68b290d99f9cd580140475b0d0d70948eb5e /src/soc
parentbc8373830128ff2991c1a8e9ff3e4255deefe746 (diff)
downloadcoreboot-fc932374a2860addbdf00dc3bd141b556508b8f3.tar.xz
soc/intel/tigerlake: Configure IOM_TYPEC_SW_CONFIGURATION_3
FSP UPD TcssAuxOri is used for setting the IOM_TYPEC_SW_CONFIGURATION_3. Configure TcssAuxOri to retimer enabled on the port 2 Type-C port. This setting informs the SoC that a retimer is taking care of SBU orientation therefore it does not need to do any flipping. The IOM_TYPEC_SW_CONFIGURATION_3 is a bitfield that controls the aux orientation settings for the Type-C ports. The TGL EDS describes this setting and what each bit represents. Reference section 3.6.5 in TGL EDS #575681 BUG=b:145943811 BRANCH=none TEST=Boot to OS and check Type-C port1 Display on volteer, Connecting Type-C display should work regardless of Type-C cable orientation. Change-Id: Iae356113cbdc72983f800060b1ebebe3c66b9daf Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39459 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/tigerlake/chip.h9
-rw-r--r--src/soc/intel/tigerlake/fsp_params_tgl.c1
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 1d4bd5fa5a..64c13ce22e 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -232,6 +232,15 @@ struct soc_intel_tigerlake_config {
uint8_t TcssXdciEn;
/*
+ * SOC Aux orientation override:
+ * This is a bitfield that corresponds to up to 4 TCSS ports on TGL.
+ * Even numbered bits (0, 2, 4, 6) control the retimer being handled by SOC.
+ * Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines
+ * on the motherboard.
+ */
+ uint16_t TcssAuxOri;
+
+ /*
* Override GPIO PM configuration:
* 0: Use FSP default GPIO PM program,
* 1: coreboot to override GPIO PM program
diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index a8be407d23..8e9787b12b 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -104,6 +104,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
else
params->PeiGraphicsPeimInit = 0;
+ params->TcssAuxOri = config->TcssAuxOri;
for (i = 0; i < 8; i++)
params->IomTypeCPortPadCfg[i] = 0x09000000;