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authorSubrata Banik <subrata.banik@intel.com>2019-04-29 12:37:27 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-05-02 06:02:40 +0000
commitff9104eae3512e554b4790b40b0bdd3fca2036b3 (patch)
treeb5f1fd9a80151dab0150bcd2d395a858dd529fe2 /src/soc
parentd32a4930910dbe5dea47777902fcb966a4854114 (diff)
downloadcoreboot-ff9104eae3512e554b4790b40b0bdd3fca2036b3.tar.xz
soc/intel/icelake: Clear PMCON status bits
This patch ports CB:31902 changes from CNL to ICL. The prev_sleep_state value was showing 5 even after warm reboot, once the SUS_PWR_FLR bit is being set. This bit was not being cleared. Hence clearing the PMCON status bits. Change-Id: Ia07aa17b4491216a277c36edfe6ed2aa489287c6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32503 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/icelake/finalize.c2
-rw-r--r--src/soc/intel/icelake/include/soc/pm.h3
-rw-r--r--src/soc/intel/icelake/pmutil.c14
3 files changed, 19 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c
index c1e6dd0d4a..e061cda2f0 100644
--- a/src/soc/intel/icelake/finalize.c
+++ b/src/soc/intel/icelake/finalize.c
@@ -87,6 +87,8 @@ static void pch_finalize(void)
}
pch_handle_sideband(config);
+
+ pmc_clear_pmcon_sts();
}
static void soc_finalize(void *unused)
diff --git a/src/soc/intel/icelake/include/soc/pm.h b/src/soc/intel/icelake/include/soc/pm.h
index 9caf49fa9a..44888ec747 100644
--- a/src/soc/intel/icelake/include/soc/pm.h
+++ b/src/soc/intel/icelake/include/soc/pm.h
@@ -168,5 +168,8 @@ uint16_t smbus_tco_regs(void);
/* Set the DISB after DRAM init */
void pmc_set_disb(void);
+/* Clear PMCON status bits */
+void pmc_clear_pmcon_sts(void);
+
#endif /* !defined(__ACPI__) */
#endif
diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c
index 96ff52d122..e1b1665368 100644
--- a/src/soc/intel/icelake/pmutil.c
+++ b/src/soc/intel/icelake/pmutil.c
@@ -141,6 +141,20 @@ void pmc_set_disb(void)
write8(addr, disb_val);
}
+void pmc_clear_pmcon_sts(void)
+{
+ uint32_t reg_val;
+ uint8_t *addr;
+ addr = pmc_mmio_regs();
+
+ reg_val = read32(addr + GEN_PMCON_A);
+ /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
+ * while retaining MS4V write-1-to-clear bit */
+ reg_val &= ~(MS4V);
+
+ write32((addr + GEN_PMCON_A), reg_val);
+}
+
/*
* PMC controller gets hidden from PCI bus
* during FSP-Silicon init call. Hence PWRMBASE