diff options
| author | V Sowmya <v.sowmya@intel.com> | 2017-09-12 14:52:12 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-13 16:18:47 +0000 |
| commit | 3670cc1bad12522e3f9eb86d923c52d4016f90e9 (patch) | |
| tree | 9a49a557a06f8af1771a7eebac33b79cd3cf7282 /src/soc | |
| parent | e1bdc6aa16f9032f04f48b4b88b8f795dbea7a44 (diff) | |
| download | coreboot-3670cc1bad12522e3f9eb86d923c52d4016f90e9.tar.xz | |
intel/common/acpi: Use UART_BASE_0_ADDR macro for LPSS UART
This patch fixes the build issue by replacing UART_DEBUG_BASE_ADDRESS
macro with UART_BASE_0_ADDR macro to configure LPSS UART base adress
for ACPI debug prints.
TEST= Build and boot soraka and fetch the ASL debug prints.
Change-Id: Ib31174701c56c88829ae0e725b546b66ea1ed16d
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/21513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/common/acpi/acpi_debug.asl | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/common/acpi/acpi_debug.asl b/src/soc/intel/common/acpi/acpi_debug.asl index aa7a1af577..d3860dd76c 100644 --- a/src/soc/intel/common/acpi/acpi_debug.asl +++ b/src/soc/intel/common/acpi/acpi_debug.asl @@ -58,7 +58,8 @@ Method (APRT, 1, Serialized) Store (INDX, LENG) /* Length of the String */ #if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32) - OperationRegion (UBAR, SystemMemory, UART_DEBUG_BASE_ADDRESS, 24) + OperationRegion (UBAR, SystemMemory, + UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE), 24) Field (UBAR, AnyAcc, NoLock, Preserve) { TDR, 8, /* Transmit Data Register BAR + 0x000 */ |