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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-01-08 11:09:37 +0100 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2019-01-14 09:13:01 +0000 |
| commit | 95c021b63a028e94a2f171b7e11774e2910898f9 (patch) | |
| tree | cbfccaa485f81311a7931eb3f13969bf3d61d2e7 /src/soc | |
| parent | 79131f8323e042165646991d88769f8a6a028924 (diff) | |
| download | coreboot-95c021b63a028e94a2f171b7e11774e2910898f9.tar.xz | |
intel/fsp1_0: Add option to select FSP debug level
Useful for debugging FSP.
Change-Id: I06e837cf1b051c55a531c3361e94fa1449bc8526
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c index b64efce4ae..ef6212eb4b 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c @@ -69,6 +69,8 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL)) UpdData->SerialPortType = 0; + UpdData->DebugOutputLevel = CONFIG_FSP_1_0_DEBUG_LEVEL; + /* * Memory Down */ |