summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorYu-Ping Wu <yupingso@chromium.org>2019-10-01 14:16:51 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-10-02 11:17:25 +0000
commitcf9588040d91148c2c83b5f6200687448f4f2193 (patch)
tree5106ec0cea46133030b5a4eb7016b0399be9f011 /src/soc
parent4c80425f3037d43cc45d56801e0717471cea0489 (diff)
downloadcoreboot-cf9588040d91148c2c83b5f6200687448f4f2193.tar.xz
mediatek/mt8183: Rename fields of struct sdram_params
Two fields of struct sdram_params are renamed for future CL of DRAM full calibration. Field 'impedance' is also removed. BUG=none BRANCH=none TEST=emerge-kukui coreboot Change-Id: I2f9673fd5ea2e62ee971f0d81bdd12aaf565e31c Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35738 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/mediatek/mt8183/dramc_pi_calibration_api.c4
-rw-r--r--src/soc/mediatek/mt8183/include/soc/emi.h5
2 files changed, 4 insertions, 5 deletions
diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
index fcc3b14a1e..f8b1f091ed 100644
--- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
+++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
@@ -252,8 +252,8 @@ static void dramc_cmd_bus_training(u8 chn, u8 rank, u8 freq_group,
{
u32 cbt_cs, mr12_value;
- cbt_cs = params->cbt_cs[chn][rank];
- mr12_value = params->cbt_mr12[chn][rank];
+ cbt_cs = params->cbt_cs_dly[chn][rank];
+ mr12_value = params->cbt_final_vref[chn][rank];
/* CBT adjust cs */
clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9],
diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h
index 264d91869a..15889eeca4 100644
--- a/src/soc/mediatek/mt8183/include/soc/emi.h
+++ b/src/soc/mediatek/mt8183/include/soc/emi.h
@@ -21,10 +21,9 @@
#include <soc/dramc_common_mt8183.h>
struct sdram_params {
- u32 impedance[2][4];
u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER];
- u8 cbt_cs[CHANNEL_MAX][RANK_MAX];
- u8 cbt_mr12[CHANNEL_MAX][RANK_MAX];
+ u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX];
+ u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX];
u32 emi_cona_val;
u32 emi_conh_val;
u32 emi_conf_val;