diff options
| author | Julius Werner <jwerner@chromium.org> | 2014-10-15 18:50:45 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-08 08:48:08 +0200 |
| commit | dae15a63e426230117b575f9acc504110748e98f (patch) | |
| tree | c48d9676dd876b85b22d70ea1436211766e18aef /src/soc | |
| parent | 108548a42aa3a255bd84247549cd1bf406a152f1 (diff) | |
| download | coreboot-dae15a63e426230117b575f9acc504110748e98f.tar.xz | |
rk3288: Add early SRAM mapping
Solving the DACR bug will mean that XN bits suddenly become enforced on
non-LPAE systems, and we will no longer be able to execute out of a
region mapped DCACHE_OFF. When we enable the MMU in romstage we are
still executing out of SRAM, so we would instantly kill ourselves.
Solve this issue by enabling the MMU earlier (in the bootblock) and
mapping the SRAM regions as DCACHE_WRITETHROUGH. They should really be
DCACHE_WRITEBACK, but it looks like there might be hardware limitations
in the Cortex-A12 cache architecture that prevent us from doing so.
Write-through mappings are equivalent to normal non-cacheable on the A12
anyway, and by using this attribute we don't need to introduce a new
DCACHE_OFF_BUT_WITHOUT_XN_BIT type in our API. (Also, using normal
non-cacheable might still have a slight speed advantage over strongly
ordered since it should fetch whole cache lines at once if the processor
finds enough accesses it can combine.)
CQ-DEPEND=CL:223783
BUG=chrome-os-partner:32118
TEST=None (depends on follow-up CL)
Change-Id: I1e5127421f82177ca11af892b1539538b379625e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e7b079f4b6a69449f3c7cc18ef0e1704f2006847
Original-Change-Id: I53e827d95acc2db909f1251de78d65e295eceaa7
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/223782
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9342
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/rockchip/rk3288/bootblock.c | 11 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3288/memlayout.ld | 3 |
2 files changed, 13 insertions, 1 deletions
diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c index eec3456613..b2f5bd9553 100644 --- a/src/soc/rockchip/rk3288/bootblock.c +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -17,10 +17,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/cache.h> #include <arch/io.h> #include <bootblock_common.h> #include <console/console.h> #include <soc/rockchip/rk3288/grf.h> +#include <symbols.h> #include "addressmap.h" #include "timer.h" #include "clock.h" @@ -41,4 +43,13 @@ static void bootblock_cpu_init(void) } rkclk_init(); + + mmu_init(); + /* Start with a clean slate. */ + mmu_config_range(0, 4096, DCACHE_OFF); + /* SRAM is tightly wedged between registers, need to use subtables. Map + * write-through as equivalent for non-cacheable without XN on A17. */ + mmu_config_range_kb((uintptr_t)_sram/KiB, + _sram_size/KiB, DCACHE_WRITETHROUGH); + dcache_mmu_enable(); } diff --git a/src/soc/rockchip/rk3288/memlayout.ld b/src/soc/rockchip/rk3288/memlayout.ld index 6faec63ba5..2ddb6a6077 100644 --- a/src/soc/rockchip/rk3288/memlayout.ld +++ b/src/soc/rockchip/rk3288/memlayout.ld @@ -34,7 +34,8 @@ SECTIONS SRAM_START(0xFF700000) TTB(0xFF700000, 16K) - BOOTBLOCK(0xFF704004, 16K - 4) + BOOTBLOCK(0xFF704004, 15K - 4) + TTB_SUBTABLES(0xFF707c00, 1K) VBOOT2_WORK(0xFF708000, 16K) OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C000, 40K) PRERAM_CBFS_CACHE(0xFF716000, 4K) |