diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-09-05 10:27:12 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-09-09 19:35:20 +0000 |
| commit | e5bad5cd3d828eba06f1db66f43948f966e7b0e0 (patch) | |
| tree | 57223c791720e2aa2137f386b43580bb14e23cc5 /src/soc | |
| parent | 14714e1303a420f9e0bf0bb5bba2efaae2c52efb (diff) | |
| download | coreboot-e5bad5cd3d828eba06f1db66f43948f966e7b0e0.tar.xz | |
verstage: use common program.ld for linking
There's no reason to have a separate verstage.ld now
that there is a unified stage linking strategy. Moreover
verstage support is throughout the code base as it is
so bring in those link script macros into the common
memlayout.h as that removes one more specific thing a
board/chipset needs to do in order to turn on verstage.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=None
Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd
Signed-off-by: Aaron Durbin <adubin@chromium.org>
Reviewed-on: http://review.coreboot.org/11516
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc')
9 files changed, 0 insertions, 9 deletions
diff --git a/src/soc/broadcom/cygnus/include/soc/memlayout.ld b/src/soc/broadcom/cygnus/include/soc/memlayout.ld index 5e149b4c4d..237ffc6203 100644 --- a/src/soc/broadcom/cygnus/include/soc/memlayout.ld +++ b/src/soc/broadcom/cygnus/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index 366b20ac91..59e30179f5 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/marvell/bg4cd/include/soc/memlayout.ld b/src/soc/marvell/bg4cd/include/soc/memlayout.ld index 15c09d96a1..45835e20e2 100644 --- a/src/soc/marvell/bg4cd/include/soc/memlayout.ld +++ b/src/soc/marvell/bg4cd/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld index 2312cc93e3..561833df16 100644 --- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld index 0f98fd2b3b..a8164a91a4 100644 --- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld index c140e013d9..dee67980d0 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld index cf417bac31..ad0977ae75 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld @@ -19,7 +19,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld index 0b759327de..b96923e677 100644 --- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld index 3b5b034d2a..4469078969 100644 --- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> |