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| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-11-02 12:14:06 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-11 10:26:14 +0000 |
| commit | e919390f4735a762234630ab7e0807c14de45421 (patch) | |
| tree | 00a607d365f06c75fc7f34ee7ef8a2c6b0d0f042 /src/soc | |
| parent | 93d215cb05a05464fef14f26f638341da2ce3d59 (diff) | |
| download | coreboot-e919390f4735a762234630ab7e0807c14de45421.tar.xz | |
soc/intel/icelake: add soc implementation for ETR address API
Add soc implementation for the new ETR address API.
Change-Id: I8383a60c2c4988948ab8b3e9a54330269d217868
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36568
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/icelake/pmutil.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index c20da5018a..8efd426606 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -170,6 +170,11 @@ uintptr_t soc_read_pmc_base(void) return (uintptr_t)pmc_mmio_regs(); } +uint32_t *soc_pmc_etr_addr(void) +{ + return (uint32_t *)(soc_read_pmc_base() + ETR); +} + void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_icelake_config *config; |