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authorAndrey Petrov <andrey.petrov@intel.com>2016-04-23 14:28:21 -0700
committerAaron Durbin <adurbin@chromium.org>2016-05-18 07:05:00 +0200
commit0e46307574befc7dab190438692c497b57c820c2 (patch)
tree6238b7947754e4b7fc415c1ffc2db97365d826cb /src/soc
parent5ede3d8ccebde6f26c6b24f6458e57d99d5f3957 (diff)
downloadcoreboot-0e46307574befc7dab190438692c497b57c820c2.tar.xz
soc/intel/apollolake: Work around FSP-M CAR layout
As of now FSP-M can not be relocated and it can not be instructed to use a specific resource for temporary memory. As result coreboot is forced to use CAR layout dictated by default FSP-M configuration. Change CAR size to 1MiB, link romstage at such CAR address so it doesn't overlap with FSP-M's default heap/stack. Change-Id: I56f78f043099dc835e294dbc081d7506bfad280d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14804 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/apollolake/Kconfig4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 7bbc6daa45..5d936ae8b3 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -73,7 +73,7 @@ config DCACHE_RAM_BASE
config DCACHE_RAM_SIZE
hex "Length in bytes of cache-as-RAM"
- default 0x80000
+ default 0x100000
help
The size of the cache-as-ram region required during bootblock
and/or romstage.
@@ -116,7 +116,7 @@ config X86_TOP4G_BOOTMEDIA_MAP
config ROMSTAGE_ADDR
hex
- default 0xfef2e000
+ default 0xfef3e000
help
The base address (in CAR) where romstage should be linked