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authorShreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>2020-09-03 14:37:53 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-09-14 07:02:44 +0000
commit121bc7a674d02d6cab9128ce573b88fc2533dea4 (patch)
tree37d9f79d75ace880ab78ceb98f176e40ba7aa40f /src/soc
parentc1d227d3120470a9e0b0d9d6f58d334782117820 (diff)
downloadcoreboot-121bc7a674d02d6cab9128ce573b88fc2533dea4.tar.xz
soc/intel/tigerlake: Select USE_CAR_NEM_ENHANCED_V2 for tigerlake
Selects Cache QoS mask MSR programming flow for Tigerlake SoC. BUG=b:145958015 TEST= Build and boot to Chrome OS on TGL-UP3 RVP. Recipe used: 1. Patch https://review.coreboot.org/c/coreboot/+/43494 that implements calculation of CQOS mask dynamically based on stack size usage & incorporates Tigerlake SoC specific programming flow. 2. QS Engineering Microcode based on 0x56 Official Microcode with LLC CQOS change. 3. QS SoC Part Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Change-Id: I602d93eb4f8243ec49993b00691140d9a6cf5733 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/tigerlake/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index cdec3ef999..826f8af467 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -25,7 +25,7 @@ config CPU_SPECIFIC_OPTIONS
select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SMI_HANDLER
select IDT_IN_EVERY_STAGE
- select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED
+ select USE_CAR_NEM_ENHANCED_V2
select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
select IOAPIC