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authorDeepa Dinamani <deepad@codeaurora.org>2015-01-12 11:57:09 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-17 09:59:08 +0200
commit1c2748d113014e7e675e6ece17c6e916a6a4ec7d (patch)
tree9c2369fc09a437eb85c9b2391addd9a9f0d0b7a8 /src/soc
parentefe279d422fcdae72f9ad54b348aa445a8e45666 (diff)
downloadcoreboot-1c2748d113014e7e675e6ece17c6e916a6a4ec7d.tar.xz
ipq806x: Add support for mmu in bootblock.
move mmu setup from RAM stage to boot block Enabling mmu earlier, helps speed up the boot time. BRANCH=storm BUG=chrome-os-partner:35024 TEST=Verified the mmu table dump matches the programmed values. Change-Id: I8f581538d5dfd0d78538c9fe50f689d54b740685 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fb799a6d61f9c2f478434a71584d0edb94af4b59 Original-Change-Id: I110497875002a88add7eb4312a70c0de8c28bc4f Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/247120 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Trevor Bourget <tbourget@codeaurora.org> Reviewed-on: http://review.coreboot.org/9756 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/qualcomm/ipq806x/include/soc/memlayout.ld5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
index 7ac066280b..bfb4450a43 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
@@ -1,6 +1,7 @@
/*
* This file is part of the coreboot project.
*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
@@ -24,6 +25,7 @@
SECTIONS
{
+ REGION(rpm, 0x00020000, 160K, 8K)
SRAM_START(0x2A000000)
/* This includes bootblock image, can be reused after bootblock starts */
/* UBER_SBL(0x2A000000, 48K) */
@@ -49,8 +51,9 @@ SECTIONS
* availale, which means CBFS cache must be in SRAM, which in turn means
* that PRERAM_CBFS_CACHE description can not be used here.
*/
- CBFS_CACHE(0x2A044000, 96K)
+ CBFS_CACHE(0x2A044000, 93K)
#endif
+ TTB_SUBTABLES(0x2A05B800, 2K)
TTB(0x2A05C000, 16K)
SRAM_END(0x2A060000)