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authorStefan Reinauer <stefan.reinauer@coreboot.org>2015-11-18 15:32:27 -0800
committerMartin Roth <martinroth@google.com>2015-12-04 17:26:26 +0100
commit1d05731e11d7fb48e940e4c40dfaf1d1a88d7bc8 (patch)
treeefeb79fdd8c3146fd2f1f56dd14c0565f5a5ae49 /src/soc
parentcd920bf1c07b35d497e4f16656cfcebe45aaf132 (diff)
downloadcoreboot-1d05731e11d7fb48e940e4c40dfaf1d1a88d7bc8.tar.xz
braswell/skylake: Add FspUpdVpd.h to fix compilation
Imported from cros repo 18ae19c Change-Id: Ib88ac9b37d2f86d323b9a04cb17a5a490c61ff5b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12467 Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/braswell/Makefile.inc1
-rw-r--r--src/soc/intel/skylake/Makefile.inc1
2 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index 426f3596b0..54b9c6a3e6 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -54,6 +54,7 @@ smm-y += tsc_freq.c
CPPFLAGS_common += -I$(src)/soc/intel/braswell/
CPPFLAGS_common += -I$(src)/soc/intel/braswell/include
+CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/braswell
CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 682f90d023..e824f2a485 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -73,6 +73,7 @@ smm-$(CONFIG_UART_DEBUG) += uart_debug.c
CPPFLAGS_common += -I$(src)/soc/intel/skylake
CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
+CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake
# Currently used for microcode path.
CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)