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authorSridhar Siricilla <sridhar.siricilla@intel.com>2020-02-06 14:21:49 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-02-12 06:13:08 +0000
commit3d27705d2741d9406409e8f18c4b4b47ca3e5a1a (patch)
tree49811872e72914d247d0963ae9fda98860f5a277 /src/soc
parentf538d74e9cf27d3353b3c1d56cb5be42c207ad84 (diff)
downloadcoreboot-3d27705d2741d9406409e8f18c4b4b47ca3e5a1a.tar.xz
soc/intel/{skl, common}: Move ME Firmware SKU Types to common code
1. Move ME firmware SKU types into common code. 2. Define ME_HFS3_FW_SKU_CUSTOM SKU. TEST=Verified on hatch & soraka. Change-Id: Iaa4cf8d5b41c1008da1e7aa63b5a6960bb9a727b Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/common/block/include/intelblocks/cse.h5
-rw-r--r--src/soc/intel/skylake/include/soc/me.h3
2 files changed, 5 insertions, 3 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index aff330a815..6f8f4ff34c 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -41,6 +41,11 @@
#define ME_HFS1_COM_SOFT_TEMP_DISABLE 0x3
#define ME_HFS1_COM_SECOVER_MEI_MSG 0x5
+/* ME Firmware SKU Types */
+#define ME_HFS3_FW_SKU_CONSUMER 0x2
+#define ME_HFS3_FW_SKU_CORPORATE 0x3
+#define ME_HFS3_FW_SKU_CUSTOM 0x5
+
/* HFSTS register offsets in PCI config space */
enum {
PCI_ME_HFSTS1 = 0x40,
diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h
index 30de2197f5..e8de30dde9 100644
--- a/src/soc/intel/skylake/include/soc/me.h
+++ b/src/soc/intel/skylake/include/soc/me.h
@@ -168,9 +168,6 @@ union me_hfs2 {
} __packed fields;
};
-#define ME_HFS3_FW_SKU_CONSUMER 0x2
-#define ME_HFS3_FW_SKU_CORPORATE 0x3
-
union me_hfs3 {
u32 data;
struct {